Intel CHIPSET 820E - Manual (Page 9)

Intel ® 820E Chipset
R
Design Guide 9
Figure 47. Device-Side IDE Cable Detection ........................................................................... 82
Figure 48. Connection Requirements for Primary IDE Connector ........................................... 83
Figure 49. Connection Requirements for Secondary IDE Connector ...................................... 84
Figure 50. ICH2 AC’97– Codec Connection ............................................................................ 85
Figure 51. CDC_DN_ENAB# Support Circuitry for a Single Codec on Motherboard ............... 87
Figure 52. CDC_DN_ENAB# Support Circuitry for Multi-Channel Audio Upgrade .................. 88
Figure 53. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard /
One-Codec on CNR................................................................................................ 88
Figure 54. CDC_DN_ENAB# Support Circuitry for Two-Codecs on Motherboard /
Two-Codecs on CNR.............................................................................................. 89
Figure 55. CNR Interface ......................................................................................................... 90
Figure 56. USB Data Signals ................................................................................................... 93
Figure 57. SMBUS/SMLink Interface ....................................................................................... 95
Figure 58. PCI Bus Layout Example ........................................................................................ 96
Figure 59. External Circuitry for the ICH RTC 2 ........................................................................ 97
Figure 60. Diode Circuit Connecting RTC External Battery ..................................................... 98
Figure 61. RTCRST External Circuit for ICH2 RTC................................................................. 99
Figure 62. SPKR Circuit ......................................................................................................... 101
Figure 63. Example PCI IRQ Routing .................................................................................... 102
Figure 64. ICH2 / LAN Connect Section ................................................................................ 103
Figure 65. Single-Solution Interconnect ................................................................................. 104
Figure 66. LOM/CNR Interconnect ........................................................................................ 105
Figure 67. LAN_CLK Routing Example.................................................................................. 106
Figure 68. Trace Routing ....................................................................................................... 107
Figure 69. Ground Plane Separation ..................................................................................... 109
Figure 70. Intel ® 82562EH Component Termination.............................................................. 113
Figure 71. Critical Dimensions for Component Placement .................................................... 114
Figure 72. Intel ® 82562ET/82562EM Component Termination.............................................. 116
Figure 73. Critical Dimensions for Component Placement .................................................... 117
Figure 74. Termination Plane................................................................................................. 119
Figure 75. Intel ® 82562ET/EM Disable Circuit ....................................................................... 119
Figure 76. Dual-Footprint LAN Connect Interface.................................................................. 120
Figure 77. Dual-Footprint Analog Interface............................................................................ 121
Figure 78. Decoupling Capacitor Layout................................................................................ 123
Figure 79. One Signal Layer and One Reference Plane........................................................ 157
Figure 80. Layer Switch with One Reference Plane .............................................................. 157
Figure 81. Layer Switch with Multiple Reference Planes (Same Type) ................................. 158
Figure 82. Layer Switch with Multiple Reference Planes ....................................................... 158
Figure 83. One Layer with Multiple Reference Planes........................................................... 159
Figure 84. Overdrive Region and V
REF
Guard Band............................................................... 161
Figure 85. Rising-Edge Flight Time Measurement ................................................................ 162
Figure 86. Intel ® 820E Chipset Platform Clock Distribution.................................................... 164
Figure 87. Intel ® 820E Chipset Clock Routing Guidelines 1,2 .................................................. 166
Figure 88. CK133-to-DRCG Routing Diagram....................................................................... 168
Figure 89. MCH-to-DRCG Routing Diagram.......................................................................... 169
Figure 90. Direct RDRAM* Clock Routing Dimensions.......................................................... 169
Figure 91. Differential Clock Routing Diagram (Sections A, C & D) ...................................... 171
Figure 92. Non-Differential Clock Routing Diagram (Section B) ............................................ 171
Figure 93. Termination for Direct RDRAM* Clocking Signals CFM/CFM# ............................ 171
Figure 94. DRCG Impedance Matching Network................................................................... 172
Figure 95. DRCG Layout Example......................................................................................... 173
Figure 96. DRCG+ Frequency Selection................................................................................ 176
Figure 97. 28 Ω Trace Geometry ........................................................................................... 177
Figure 98. Microstrip (a) and Stripline (b) Cross Section for 28 Ω Trace............................... 180
Figure 99. 7 mil Stack-Up (Not Routable) .............................................................................. 181