Intel(r) 820e chipset – Intel CHIPSET 820E User Manual
Page 197

5-23-2000_9:18
1
REVISION 0.5
FCPGA 2 RIMM ICH2 REFERENCE SCHEMATICS
DRAWN BY:
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
87
6
5
4
3
2
1
A
B
C
D
1
2
3
4
5
6
7
8
D
C
B
A
PCG PLATFORM DESIGN
REV:
0.5
PROJECT:
OF 40
TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD
R
PCG AE
Camino2
Note that these schematics are preliminary and are subject to change.
INTEL(R) 820E CHIPSET
T
H
ESE SCHEM
A
T
ICS ARE PRO
V
ID
E
D
“
AS I
S
” W
IT
H
N
O
W
A
RRANT
IE
S
W
H
AT
SO
EVER,
INCL
U
D
IN
G AN
Y
W
A
RRANT
Y
O
F
M
E
RCHANT
A
B
IL
IT
Y
, F
IT
N
ESS FO
R ANY
PART
ICUL
AR
P
U
R
P
OS
E
, OR
A
N
Y
W
A
R
R
A
N
T
Y
O
T
HE
RW
IS
E
A
R
IS
IN
G OU
T
O
F
P
R
O
P
OS
A
L
,
SPECI
F
IC
AT
IO
N O
R
SA
M
P
L
ES.
In
for
m
at
ion i
n
t
h
is
docum
ent
i
s
pr
ovi
ded i
n
c
onnec
ti
on w
it
h
I
n
te
l pr
oduc
ts
. N
o
l
icens
e,
express
or
im
pl
ied,
by
est
oppel
or
ot
herw
ise,
t
o
any
i
n
te
llec
tual
proper
ty
r
ight
s
i
s
gr
ant
ed by
t
h
is
doc
um
ent
.
E
x
c
ept
as provi
ded i
n
I
n
te
l's
T
e
rm
s
and C
ondi
ti
ons
of S
a
le
for suc
h
pr
oduc
ts
, I
n
te
l ass
u
m
e
s no
liabi
lit
y
w
hat
soever
, and I
n
te
l di
sc
la
im
s any
ex
pr
es
s or
i
m
pl
ied w
a
rr
ant
y
, r
e
la
ti
ng t
o
sal
e
and/
or
us
e of
I
n
te
l product
s
i
n
c
ludi
ng l
iabi
lit
y
or w
a
rr
ant
ie
s
r
e
la
ti
ng t
o
fi
tnes
s for
a
par
ti
cul
a
r pur
pos
e,
m
e
rc
hant
abi
li
ty
, or
i
n
fr
ingem
ent
of any
pat
ent
, c
opy
ri
ght
or
ot
her
i
n
te
llec
tual
pr
oper
ty
ri
ght
. I
n
te
l
pr
oduc
ts
are not
i
n
tended f
o
r use i
n
m
edi
c
a
l,
l
ife savi
ng,
or
l
ife s
u
st
ai
ni
ng appl
ic
at
ions
. I
n
te
l m
a
y
m
a
k
e
c
hanges t
o
s
peci
fi
c
at
ions and product
des
cri
p
ti
ons
at
any
t
im
e
, w
it
hout
not
ic
e.
T
he I
n
te
l 82820E
chi
p
s
e
t m
a
y
c
ont
ai
n des
ign defect
s
or
er
ror
s
k
now
n as
er
rat
a
w
h
ic
h m
a
y
caus
e
the pr
oduc
t t
o
devi
a
te
from
publ
is
hed s
peci
fi
c
at
ions.
C
u
rr
ent
c
har
ac
te
ri
z
ed err
a
ta
ar
e avai
labl
e on
reques
t.
In
te
l m
a
y
m
a
k
e
changes
t
o
spec
if
ic
at
ions
and pr
oduc
t desc
ri
p
ti
ons
at
any
t
im
e
, w
it
hout
not
ic
e.
C
opy
ri
ght
©
I
n
te
l C
o
rporat
io
n
2000.
*
T
hi
rd
-part
y
br
ands
and nam
es
ar
e t
he proper
ty
of t
hei
r r
e
s
pect
ive ow
ner
s
.
T
it
le
P
age
Co
v
e
r S
h
e
e
t
1
Bl
oc
k
D
iag
ra
m
2
P
ro
c
es
s
o
r C
o
nne
c
tor
3,
4
C
loc
k
Sy
nt
hes
iz
e
r
5
MCH
6
, 7
IC
H
2
8
, 9
FW
H
1
0
RI
MM S
o
c
k
e
ts
1
1
Supe
r I
/O
1
2
A
udi
o
13,
14
LA
N
1
5,
16,
17,
18
,
LA
N
1
9,
2
0
,21,
22
Sy
s
tem
23
A
G
P
C
onn
ec
to
r
2
4
P
C
I C
onn
ec
to
rs
25,
26
ID
E
C
onn
ec
to
rs
27
U
SB C
o
n
nec
to
rs
28
P
a
ra
lle
l P
o
rt
2
9
Ser
ia
l P
o
rt
s
3
0
Key
b
oar
d/
M
ous
e/
F
loppy
P
o
rt
s
3
1
Ga
m
e
P
o
rt
3
2
VR
M
3
3
V
o
lt
a
ge R
e
g
u
la
to
rs
34,
35
P
o
w
e
r C
onne
c
tor
36
A
G
TL
Te
rm
in
a
ti
o
n
3
7
P
C
I/
A
G
P
P
u
llups
/P
u
lld
o
w
ns
38
R
A
M
B
U
S
D
e
c
oup
ling
39
D
e
c
o
upl
in
g
40,
41
R
e
vi
si
o
n
H
is
to
ry
4
2