Intel CHIPSET 820E - Manual (Page 226)

3-20-2000_10:15
SERIAL PORTS
30
CTS1_C DTR1_C DCD1_C
RTS0_C DTR0_C RXD0_C DSR0_C
TXD1_C RXD1_C RTS1_C
U6
19 18 17 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
16 20
TXD1
12 12
DCD#1
12
RTS#1
12
RXD1
12
CTS#1
12
RI#1
12
DSR#1
12
DTR#1
DCD0_C CTS0_C TXD0_C
12
DTR#0
12
DSR#0
12
RI#0
12
CTS#0
12
RXD0
12
RTS#0
12
DCD#0 TXD0
12
U4
20 16
10 9 8 7 6 5 4 3 2 1
11 12 13 14 15 17 18 19
RI0_C
9
ICH_RI#
J6
A5 A9 A4 A8 A3 A7 A2 A6 A1
J7
4
9
8
7
6
5 3
2 10
1
DSR1_C
R69
47K RI_Q 47K
R70
10K
R17
RI_CR
CR2
1 2
3 1UF
C92
CP1 100PF
3 6
100PF CP8
4 5
CP8 100PF
7 2
CP8 100PF
3 6
100PF CP1
4 5
100PF CP8
1 8
100PF CP1
8 1
CP1 100PF
7 2
100PF CP7
8 1
100PF CP6
4 5
CP7 100PF
5 4
100PF CP7
3 6
CP6 100PF
8 1
100PF CP6
2 7
100PF CP6
6 3
Q1
1
3 2
100PF CP7
7 2
RI1_C
DRAWN BY: LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630 1900 PRAIRIE CITY ROAD
87
6
5
4
3
2
1
A B C D
1
2
3
4
5
6
7
8
D C B A
PCG PLATFORM DESIGN
REV:
0.5
PROJECT:
OF 40
TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD
R
PCG AE
Camino2
VCC12-
VCC5
VCC12
RY0 RY1 RY2 DA1 RY3 DA2 RY4 GND
VCC12
RA0 RA1 RA2 DY0 DY1 RA3 DY2 RA4
VCC-12
DA0 VCC
GD75232
RY0 RY1 RY2 DA1 RY3 DA2 RY4 GND
VCC12
RA0 RA1 RA2 DY0 DY1 RA3 DY2 RA4
VCC-12
DA0 VCC
GD75232
VCC12
VCC5
VCC12-
DB25_DB9_STK
DCD DSR RXD RTS TXD CTS DTR
RI
GND
VCC3_3SBY
BAT54C
2N7002LT1
1
3 2
COM2 is a 2x5 pin header for a cabled port.
COM1
COM2
Serial Ports