Intel CHIPSET 820E - Manual (Page 70)

Intel ® 820E Chipset
R
70 Design Guide
2.8.9. Compensation
The MCH AGP interface supports resistive buffer compensation (RCOMP). Tie the GRCOMP pin to a
40
Ω, 2% (or 39- Ω , 1%) pull-down resistor (to ground), via a 10 mil-wide, very short (<0.5 inch) trace.
2.8.10. AGP Pull-Ups
AGP control signals require pull-up resistors to V
DDQ
on the motherboard, to ensure that they maintain
stable values when no agent is actively driving the bus. The signals requiring pull-up resistors are:
• 1 × timing domain signals
 FRAME#
 TRDY#
 IRDY#
 DEVSEL#
 STOP#
 SERR#
 PERR#
 RBF#
 PIPE#
 REQ#
 WBF#
 GNT#
 ST[2:0]
It is critical that these signals be pulled up to V
DDQ
(not 3.3 V).
The trace stub to the pull-up resistor on 1 × timing domain signals should be kept at less than
0.5 inch, to avoid signal reflections from the stub.
The strobe signals require pull-up/pull-downs on the motherboard, to ensure that they maintain
stable values when no agent is driving the bus.
Note: INTA# and INTB# should be pulled to 3.3 V, not V
DDQ
.
• 2 Ч /4 Ч timing domain signals
 AD_STB[1:0] (pull-up to V
DDQ
)
 SB_STB (pull-up to V
DDQ
)
 AD_STB[1:0]# (pull-down to ground)
 SB_STB# (pull-down to ground)
The trace stub to the pull-up/pull-down resistor on 2 Ч /4 Ч timing domain signals should be kept to
less than 0.1 inch, to avoid signal reflections from the stub.
The pull-up/pull-down resistor value requirements are shown in the following table.
R
MIN
R
MAX
4 k Ω 16 k Ω
The recommended AGP pull-up/pull-down resistor value is 8.2 k Ω .