Intel CHIPSET 820E - Manual (Page 106)

Intel ® 820E Chipset
R
106 Design Guide
Figure 67. LAN_CLK Routing Example
LAN_RXD0 LAN_CLK
2.22.1.5. Crosstalk Consideration
Crosstalk-induced noise must be carefully minimized. Crosstalk is the principal cause of timing skews
and is the largest part of the t
RMATCH
skew parameter.
2.22.1.6. Impedances
Motherboard impedances should be controlled to minimize the effect of any mismatch between the
motherboard and an add-in card. An impedance of 60
Ω ± 15% is strongly recommended. Otherwise, the
signal integrity requirements may be violated.
2.22.1.7. Line Termination
Line termination mechanisms are not specified for the LAN connect interface. Slew rate-controlled
output buffers provide acceptable signal integrity by controlling signal reflection, overshoot/undershoot,
and ringback. A 33-
Ω series resistor can be installed at the driver side of the interface, if the developer
has concerns about overshoot/undershoot. Note that the receiver must allow for any drive strength and
board impedance characteristic within the specified ranges.