Intel CHIPSET 820E User Manual
Page 214
18
3-20-2000_10:29
R254
120
1%
19,20,21
LAN_RDM
19,20,21
LAN_RDP
16,17
LAN_RESET
16
LAN_RXD2
16,17
LAN_CLK
16,17
LAN_RXD0
16
LAN_RXD1
19,20
LAN_ACTLED
17,19,20
LAN_LILED
19,20
LAN_TDM
19,20
LAN_TDP
16,17
LAN_TXD0
16
LAN_TXD1
16
LAN_TXD2
17,21
LAN_CLK_X1
17,21
LAN_CLK_X2
17
PHAD_ISOL_PINS
1%
549
R259
220
R319
R258
100
1%
17,19,20
LAN_SPEEDLED
U25
40
48
33
13
8
24
38
22
20
18
6
3
35
34
39
37
42
36
25
1
23
19
17
14
12
9
2
7
10
11
15
16
32
31
27
21
5
4
47
26
41
28
30
29
46
45
44
43
1%
619
R320
DRAWN BY:
LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630
1900 PRAIRIE CITY ROAD
8
765
43
21
A
B
C
D
1
2
3
4
5
6
7
8
D
C
B
A
PCG PLATFORM DESIGN
REV:
0.5
PROJECT:
OF 40
TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD
R
PCG AE
Camino2
VCC3_3SBY
VCC3_3SBY
JTXD_0
JTXD_1
JTXD_2
X1
ISOL_TEX
ISOL_TCK
ISOL_TI
ADV10
TOUT
X2
RBIAS10
RBIAS100
TESTEN
LILED
SPEEDLED
ACTLED
RDN
RDP
TDN
TDP
VCCA-7
VCCA-2
VCCT-9
VCCT-1
2
VCCT-1
4
VCCT-1
7
VCCR-1
9
VCCR-2
3
VCC-1
VCC-2
5
VCCP-3
6
JRESET
JRXD_2
JCLK
JRXD_0
JRXD_1
VSSA-3
VSSA2-6
VSS-1
8
VSSR-2
0
VSSR-2
2
VSSP-3
8
VSS-2
4
VSS-8
VSS-1
3
VSSP-3
3
VSS-4
8
VCCP-4
0
LAN (
8
2
5
6
2
ET
)
LAN (
82
56
2
ET
/E
M
)
EMPTY ALL COMPONENTS ON THIS PAGE
NOTE: FOR HOME LAN CONFIGURATION