Intel CHIPSET 820E - Manual (Page 136)

Intel ® 820E Chipset
R
136 Design Guide
# Layout Recommendations Yes No Comments
20 Isolate I/O signals from high-speed signals. To minimize crosstalk
21 Place the 82562ET/EM part more than 1.5 inches
from any board edge. This minimizes the potential of EMI
radiation problems.
22 Verify the EEPROM size.
82562ET : 64 word
82562EM : 256 word
TheIntel ® 82562EM requires a
larger EEPROM to store the alert
envelope and other configuration
information.
23 Place at least one bulk capacitor ( ≥ 4.7 µF is OK)
on each side of the 82562ET/EM.
Research and development has
shown that this is a robust design.
24 Place decoupling caps (0.1 µF) as close as
possible to the 82562ET/EM.
25 RBIAS10 and RBIAS100 resistors should have 1%
values. These biasing resistors require 1%
accuracy. Note that the values
shown on the reference schematic
are the recommended starting
values. Fine tuning (via IEEE
conformance testing) is required
for each new design.
Table 47. AC’97
# Layout Recommendations Yes No Comments
1 Z
0
AC’97 = 60 Ω ± 15%
2 5 mil trace width, 5 mil spacing between traces
3 Max. trace length ICH2/codec/CNR = 14 inches
Table 48. ICH2 Decoupling
# Layout Recommendations Yes No Comments
1 3.3Vcore : Six 0.1 µF caps
2 3.3VSBY : One 0.1 µF cap
3 CPUI/F(VCCcore) : One 0.1 µF cap
4 1.8Vcore : Two 0.1 µF caps
5 1.8VSBY : One 0.1 µF cap
6 5VREF : One 0.1 µF cap
7 5VREFSBY : One 0.1 µF cap
8 Place decoupling caps as close as possible to the
ICH2 (~200 mils).