Maxim Integrated MAXQ622 User Manual
Maxim Integrated Hardware
This manual is related to the following products:
Table of contents
Document Outline
- TABLE OF CONTENTS
- SECTION 1: Overview
- SECTION 2: Architecture
- 2.1 Instruction Decoding
- 2.2 Register Space
- 2.3 Memory Organization
- 2.4 Memory Management Unit
- 2.5 Memory Mapping
- 2.6 Memory Protection
- 2.6.1 Rules for System Software
- 2.6.2 Privilege Exception Interrupt
- 2.6.3 Memory Access Protection Impact on Data Pointers (and Code Pointer)
- 2.6.4 Debugging
- 2.6.5 Enabling Memory Protection
- 2.6.6 Reset Procedure and Setup of Memory Protection
- 2.6.7 Loader Access Control
- 2.6.8 Disabling MAXQ612/MAXQ622-Specific Memory Access Features
- 2.7 Clock Generation
- 2.8 Wake-Up Timer
- 2.9 Interrupts
- 2.10 Operating Modes
- 2.11 Reset Mode
- 2.12 Power-Management Mode
- 2.13 Stop Mode
- SECTION 3: Programming
- 3.1 Addressing Modes
- 3.2 Prefix Operations
- 3.3 Reading and Writing Registers
- 3.3.1 Loading an 8-Bit Register with an Immediate Value
- 3.3.2 Loading a 16-Bit Register with a 16-Bit Immediate Value
- 3.3.3 Moving Values Between Registers of the Same Size
- 3.3.4 Moving Values Between Registers of Different Sizes
- 3.3.5 8-Bit Destination ← Low Byte (16-Bit Source)
- 3.3.6 8-Bit Destination ← High Byte (16-Bit Source)
- 3.3.7 16-Bit Destination ← Concatenation (8-Bit Source, 8-Bit Source)
- 3.3.8 Low (16-Bit Destination) ← 8-Bit Source
- 3.3.9 High (16-Bit Destination) ← 8-Bit Source
- 3.4 Reading and Writing Register Bits
- 3.5 Using the Arithmetic and Logic Unit
- 3.5.1 Selecting the Active Accumulator
- 3.5.2 Enabling Autoincrement and Autodecrement
- 3.5.3 ALU Operations Using the Active Accumulator and a Source
- 3.5.4 ALU Operations Using Only the Active Accumulator
- 3.5.5 ALU Bit Operations Using Only the Active Accumulator
- 3.5.6 Example: Adding Two 4-Byte Numbers Using Autoincrement
- 3.6 Processor Status Flag Operations
- 3.7 Controlling Program Flow
- 3.8 Accessing the Stack
- 3.9 Accessing Data Memory
- 3.10 Using the Watchdog Timer
- SECTION 4: System Register Description
- SECTION 5: Peripheral Register Modules
- SECTION 6: General-Purpose I/O Module
- SECTION 7: Timer/Counter Type B
- SECTION 8: IR Timer
- SECTION 9: Serial I/O Module
- SECTION 10: Serial Peripheral Interface (SPI) Module
- SECTION 11: I2C Interface
- SECTION 12: Universal Serial Bus (USB) Interface
- 12.1 USB SIE Endpoint Description
- 12.2 USB SIE Features
- 12.3 USB Peripheral Register Descriptions
- 12.4 USB SIE Internal Register Descriptions
- 12.4.1 Function Address Register (FNADDR)
- 12.4.2 USB Control Register (USBCN)
- 12.4.3 USB Configuration Register (USBCFG)
- 12.4.4 USB Interrupt Enable Register (USBIEN)
- 12.4.5 USB Interrupt Register (USBINT)
- 12.4.6 Endpoint Interrupt Enable Register (EPIEN)
- 12.4.7 Endpoint Interrupt Register (EPINT)
- 12.4.8 Endpoint Stall Register (EPSTL)
- 12.4.9 Endpoint NAK Register (EPNAK)
- 12.4.10 Endpoint Clear Data Toggle Register (EPCTG)
- 12.4.11 Endpoint 0 Byte Count Register (EP0BC)
- 12.4.12 Endpoint 1 OUT Byte Count Register (EP1BC)
- 12.4.13 Endpoint 2 IN Byte Count Register (EP2BC)
- 12.4.14 Endpoint 3 IN Byte Count Register (EP3BC)
- 12.4.15 Endpoint 0 Buffer Register (EP0BUF)
- 12.4.16 Endpoint 1 Buffer Register (EP1BUF)
- 12.4.17 Endpoint 2 Buffer Register (EP2BUF)
- 12.4.18 Endpoint 3 Buffer Register (EP3BUF)
- 12.4.19 Setup Data Buffer Register (SUDBUF)
- 12.5 USB Examples
- SECTION 13: Test Access Port (TAP)
- SECTION 14: In-Circuit Debug Mode
- SECTION 15: In-System Programming (JTAG)
- SECTION 16: MAXQ612/MAXQ622 Instruction Set Summary
- SECTION 17: Utility ROM
- APPENDIX 1: Data Pointer Usage Examples
- INDEX
- REVISION HISTORY