Maxim Integrated MAXQ622 - Manual (Page 35)

MAXQ612/MAXQ622 User’s Guide
Maxim Integrated 2-31
2.11.3 Watchdog Timer Reset
The watchdog timer is a programmable hardware timer that can be set to reset the processor in the case of a soft-
ware lockup or other unrecoverable error . Once the watchdog is enabled in this manner, the processor must reset the
watchdog timer periodically to avoid a reset . If the processor does not reset the watchdog timer before it elapses, the
watchdog initiates a reset state .
If the watchdog resets the processor, it remains in reset for four clock cycles . Once the reset condition is removed, the
processor begins executing program code from utility ROM at address 8000h . When a reset occurs due to a watch-
dog timeout, the watchdog timer reset flag in the WDCN register is set to 1 and can only be cleared by software . User
software can examine this bit following a reset to determine if that reset was caused by a watchdog timeout .
2.11.4 Internal System Reset
The MAXQ612/MAXQ622 can incorporate functions that logically warrant the ability to generate an internal system
reset . This reset generation capability is assessed by MAXQ612/MAXQ622 function based upon its expected use .
In-system programming is a prime example of functionality that benefits by having the ability to reset the device . The
exact in-system programming protocol is somewhat device- and interface-specific, however, it is expected that, upon
completion of in-system programming, many users will want the ability to reset the system . This internal (software-
triggered) reset generation capability is possible following in-system programming .
2.12 Power-Management Mode
There are two major sources of power dissipation in CMOS circuitry . The first is static dissipation caused by continu-
ous leakage current . The second is dynamic dissipation caused by transient switching current required to charge and
discharge load capacitors as well as short-circuit current produced by momentary connections between V
DD
and
ground during gate switching .
Usually it is the dynamic switching power dissipation that dominates the total power consumption, and this power dis-
sipation (P
D ) for a CMOS circuit can be calculated in terms of load capacitance (C L ), power-supply voltage (V DD ),
and operating frequency (f) as:
P D = C L O V DD2 O f
Capacitance and supply voltage are technology dependent and relatively fixed . However, the operating frequency
determines the clock rate, and the required clock rate can be different from application to application depending on
the amount of processing power required .
If an external crystal or oscillator is being used, the operating frequency can be adjusted by changing external compo-
nents . However, it could be the case that a single application can require maximum processing power at some times
and very little at others . Power-management mode allows an application to reduce its clock frequency and, therefore,
its power consumption under software control .
Power-management mode is invoked by setting the PMME bit to 1 . Once this bit has been set, one system clock cycle
occurs every 256 oscillator cycles . All operations continue as normal in this mode, but at the reduced clock rate . Power-
management mode can be deactivated by clearing the PMME bit to 0; the PMME bit is also cleared automatically to
0 by any reset condition .
To avoid data loss, the PMME bit cannot be set while the USART or SPI ports are either transmitting or receiving, or
while an external interrupt is waiting to be serviced . Attempts to set the PMME bit under these conditions result in a
no-op .
2.12.1 Switchback
When power-management mode is active, the MAXQ612/MAXQ622 operate at a reduced clock rate . Although execu-
tion continues as normal, peripherals that base their timing on the system clock such as the USART module and the SPI
module might be unable to operate normally or at a high enough speed for proper application response . Additionally,
interrupt latency is greatly increased .
The switchback feature is used to allow a processor running under power-management mode to switch back to normal
mode quickly under certain conditions that require rapid response . Switchback is enabled by setting the SWB bit to 1 .