Maxim Integrated MAXQ622 - Manual (Page 191)

MAXQ612/MAXQ622 User’s Guide
13-4 Maxim Integrated
When the parallel instruction register (IR[2:0]) is updated, the TAP controller decodes the instruction and performs any
necessary operations, including activation of the data shift register to be used for the particular instruction during data
register shift sequences (DR-scan) . The length of the activated shift register depends upon the value loaded to the
instruction register (IR[2:0]) . The supported instruction register encodings and associated data register selections are
shown in Table 13-3 .
The extest (IR[2:0] = 000b) and sample/preload (IR[2:0] = 001b) instructions are mandated by the JTAG standard,
however, the MAXQ612/MAXQ622 microcontrollers do not intend to make practical use of these instructions . Hence,
these instructions are treated as no operations but can be entered into the instruction register without affecting the
on-chip system logic or pins, and does not change the existing serial data register selection between TDI and TDO .
The bypass (IR[2:0] = 011b, 101b, or 111b) instruction is also mandated by the JTAG standard . The bypass instruc-
tion is fully implemented by the MAXQ612/MAXQ622 microcontrollers to provide a minimum length serial data path
between the TDI and the TDO pins . This is accomplished by providing a single-cell bypass shift register . When the
instruction register is updated with the bypass instruction, a single bypass register bit is connected serially between
TDI and TDO in the shift-DR state . The instruction register automatically defaults to the bypass instruction when the
TAP is in the test-logic-reset state . The bypass instruction has no effect on the operation of the on-chip system logic .
The debug (IR[2:0] = 010b) and system programming (IR[2:0] = 100b) instructions are private instructions that are
intended solely for in-circuit debug and in-system programming operations, respectively . If the instruction register is
updated with the debug instruction, a 10-bit serial shift register is formed between the TDI and TDO pins in the shift-
DR state . If the system programming instruction is entered into the instruction register (IR[2:0]), a 3-bit serial data shift
register is formed between the TDI and TDO pins in the shift-DR state .
Table 13-2. Instruction Register Content vs. TAP Controller State
Table 13-3. Instruction Register (IR[2:0]) Encodings
TAP CONTROLLER
STATE
INSTRUCTION SHIFT REGISTER
PARALLEL (3-BIT) INSTRUCTION REGISTER
(IR[2:0])
Test-Logic-Reset Undefined Set to bypass (011b) instruction
Capture-IR Load 001b at the rising edge of TCK Retain last state
Shift-IR
Input data through TDI and shift towards TDO at
the rising edge of TCK
Retain last state
Exit1-IR
Exit2-IR
Pause-IR
Retain last state Retain last state
Update-IR Retain last state Load from shift register at the falling edge of TCK
All other states Undefined Retain last state
IR[2:0] INSTRUCTION FUNCTION
SERIAL DATA SHIFT REGISTER
SELECTION
000 Extest No operation Unchanged; retain previous selection
001 Sample/Preload No operation Unchanged; retain previous selection
010 Debug In-circuit debug mode 10-bit shift register
011 Bypass No operation (default) 1-bit shift register
100 System Programming Bootstrap function 3-bit shift register
101 Bypass No operation (default) 1-bit shift register
110 Reserved Reserved Reserved
111 Bypass No operation (default) 1-bit shift register