Maxim Integrated MAXQ622 - Manual (Page 31)

MAXQ612/MAXQ622 User’s Guide
Maxim Integrated 2-27
2) The IPS bits are set to 11b to re-enable interrupt handling .
3) The instruction pointer is set to the return address that was popped off the stack .
4) The CPU continues execution of the main program .
Pending interrupt requests do not interrupt a RETI instruction; a new interrupt is serviced after first being acknowledged
in the execution cycle that follows the RETI instruction and then after the standard one stall cycle of interrupt latency .
This means there are at least two cycles between back-to-back interrupts .
2.9.3 Synchronous vs. Asynchronous Interrupt Sources
Interrupt sources can be classified as either asynchronous or synchronous . All internal interrupts are synchronous inter-
rupts . An internal interrupt is directly routed to the interrupt handler that can be recognized in one cycle . All external
interrupts are asynchronous interrupts by nature . Asynchronous interrupt sources are passed through a three-clock
sampling/glitch filter circuit before being routed to the interrupt handler . The sampling/glitch filter circuit is running on
the undivided source clock (i .e ., before PMME, CD[1:0] controlled clock divide) such that the number of system clocks
required to recognize an asynchronous interrupt request depend upon the system clock divide ratio:
• If the system clock-divide ratio is 1, the interrupt request is recognized after three system clocks.
• If the system clock-divide ratio is 2, the interrupt request is recognized after two system clocks.
• If the system clock divide ratio is 4 or greater, the interrupt request is recognized after one system clock.
An interrupt request with pulse width less than three undivided clock cycles is not recognized .
Note that the granularity of interrupt source is at module level . Synchronous interrupts and sampled asynchronous
interrupts assigned to the same module product a single interrupt to the interrupt handler .
External interrupts, when enabled, can be used as switchback sources from power-management mode . There is no
latency associated with the switchback because the circuit is being clocked by an undivided clock source vs . the
divide-by-256 system clock . For the same reason, there is no latency for other switchback sources that do not qualify
as interrupt sources .
2.9.4 Interrupt Prioritization by Software
There are three levels of interrupt priorities: level 0 to 2 . Level 0 is the highest priority and level 2 is the lowest . All
interrupts have individual priority bits in the IPR0 register to allow each interrupt to be assigned a priority level . All inter-
rupts have a natural priority or hierarchy . In this manner, when a set of interrupts has been assigned the same prior-
ity, this natural priority hierarchy determines which interrupt is allowed to take precedence if multiple interrupts occur
simultaneously . The natural hierarchy is determined by analyzing potential interrupts in a sequential manner with the
preferred order as listed in Table 2-8 . Once an interrupt is being processed, only an interrupt with higher priority level
can preempt it . Therefore, the MAXQ612/MAXQ622 support a maximum of two levels of interrupt nesting .
For example, suppose three interrupts occur simultaneously and the assigned priorities (IVP bits) for each of the inter-
rupt sources are as follows:
• IR Timer: assigned priority level 1
• Serial Port 0: assigned priority level 2
• Timer B0: assigned priority level 2
Because simultaneous interrupts are first evaluated according to assigned priority level, the IR timer interrupt is ser-
viced first . Once the IR timer interrupt source has been cleared, the serial port 0 and timer B0 interrupt sources are
evaluated . Both of these interrupt sources have been assigned to the same priority level (level 2), so the natural prior-
ity of each source is used to determine which is serviced first . The serial port 0 interrupt is serviced first as its natural
priority is 4, whereas timer B0 has natural priority 6 . If two interrupts that are grouped under the same natural priority
occur simultaneously, the order in which handling of the interrupts occurs is left to the discretion of user code (i .e ., user
code must decide what order to check the associated interrupt flags) .
For an unhandled interrupt, the interrupt handler vectors to flash address 0x98 if the user disables any of the inter-
rupts when an interrupt is triggered or when a medium priority interrupt occurs while in stop mode . A simple “RETI” is
required to be placed at 0x98 .