Maxim Integrated MAXQ622 - Manual (Page 166)

MAXQ612/MAXQ622 User’s Guide
Maxim Integrated 11-11
11.4.4 I 2 C Interrupt Enable Register (I2CIE)
Bits 15 to 12 and 10: Reserved. Reads return 0.
Bit 11: I
2 C STOP Interrupt Enable (I2CSPIE). Setting this bit to 1 causes an interrupt to the CPU when a STOP condi-
tion is detected (I2CSPI = 1) . Clearing this bit to 0 disables a STOP detection interrupt from generating .
Bit 9: I
2 C Receiver Overrun Interrupt Enable (I2CROIE). Setting this bit to 1 causes an interrupt to the CPU when a
receiver overrun condition is detected (I2ROI = 1) . Clearing this bit to 0 disables a receiver overrun detection interrupt
from generating .
Bit 8: I
2 C General Call Interrupt Enable (I2CGCIE). Setting this bit to 1 generates an I2CGCI (general call interrupt)
to the CPU when a general call is enabled (I2CGCEN = 1) . Clearing this bit to 0 disables a general call interrupt from
generating .
Bit 7: I
2 C NACK Interrupt Enable (I2CNACKIE). Setting this bit to 1 causes an interrupt to the CPU when a NACK is
detected (I2CNACKI = 1) . Clearing this bit to 0 disables a NACK detection interrupt from generating .
Bit 6: I
2 C Arbitration Loss Enable (I2CALIE). Setting this bit to 1 causes an interrupt to the CPU when the I 2 C master
loses in an arbitration (I2CALI = 1) . Clearing this bit to 0 disables an arbitration loss interrupt from generating .
Bit 5: I
2 C Slave Address Match Interrupt Enable (I2CAMIE). Setting this bit to 1 causes an interrupt to the CPU when
the I 2 C controller detects an address that matches the I2CSLA value (I2CAMI = 1) . Clearing this bit to 0 disables an
address match interrupt from generating .
Bit 4: I
2 C Timeout Interrupt Enable (I2CTOIE). Setting this bit to 1 causes an interrupt to the CPU when a timeout
condition is detected (I2CTOI = 1) . Clearing this bit to 0 disables a timeout interrupt from generating .
Bit 3: I
2 C Clock Stretch Interrupt Enable (I2CSTRIE). Setting this bit to 1 generates an interrupt to the CPU when
the clock stretch interrupt flag is set (I2CSTRI = 1) . Clearing this bit disables a clock stretch interrupt from generating .
Bit 2: I
2 C Receive Ready Interrupt Enable (I2CRXIE). Setting this bit to 1 causes an interrupt to the CPU when the
receive interrupt flag is set (I2CRXI = 1) . Clearing this bit to 0 disables a receive interrupt from generating .
Bit 1: I
2 C Transmit Complete Interrupt Enable (I2CTXIE). Setting this bit to 1 causes an interrupt to the CPU when
the transmit interrupt flag is set (I2CTXI = 1) . Clearing this bit to 0 disables a transmit interrupt from generating .
Bit 0: I
2 C START Interrupt Enable (I2CSRIE). Setting this bit to 1 causes an interrupt to the CPU when a START condi-
tion is detected (I2CSRI = 1) . Clearing this bit to 0 disables a START detection interrupt from generating .
Register Name I2CIE
Register Description I 2 C Interrupt Enable Register
Register Address M4[03h]
Bit # 15 14 13 12 11 10 9 8
Name — — — — I2CSPIE — I2CROIE I2CGCIE
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw r rw rw
Bit # 7 6 5 4 3 2 1 0
Name I2CNACKIE I2CALIE I2CAMIE I2CTOIE I2CSTRIE I2CRXIE I2CTXIE I2CSRIE
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw