Maxim Integrated MAXQ622 User Manual
Page 23
MAXQ612/MAXQ622 User’s Guide
Maxim Integrated
2-19
This is no different for instructions that operate on data pointers . For example, a pointer to pointer move such as MOVE
@DP[1], @DP[0] first requires the read pointer to be activated . Architecturally, this strobes the chip enable and read
signals on the memory mapped to the location in DP[0] . This value is latched internally so that it is available when @
DP[0] is used as the source operand . At that time, the internally latched data is transferred to the destination register .
This functions normally when memory protection is not enabled . However if MPE is set the same code can cause a
memory protection fault . For this example let us assume the following:
1) The code is executing from RAM
2) REQUESTED_RAM_ADDRESS is defined as #0000h
3) Flash memory is located from 0000h–7FFFh
MOVE DPC, #REQUIRED_DP0_MODE
; Activates DP[0]
;
In
this
MMU
mapping,
;
addresses
0-7FFFh
are
in
Flash
;
and
*if*
the
previous
contents
; of DP[0], modified by DPC, are
; in System space, we will generate
;
a
memory fault
MOVE DP[0], #REQUESTED_RAM_ADDRESS ; Again, activates DP[0]
;
Now
we
know
that
DP[0]
;
points
to
address
0000h
;
and
in
the
current
MMU
;
mapping,
we
are
;
definitely
pointing
to
;
*and
reading
from*
;
System
space
in
flash.
;
MEMORY
FAULT
GUARANTEED
LCALL UROM_MOVEDP0
; Changes MMU mapping. In
;
this
case,
addresses
;
0-7FFFh
point
to
RAM
; actual ROM function
MOVE DP[0], DP[0]
; ACTIVATE DP[0] in RAM
;
space.
If
we
studied
;
the
above
discussion
;
carefully,
we
know
that
;
*activate*
means
*read*
MOVE GR, @DP[0]
; Transfer the latched
;
DP[0]
value
to
GR
RET ;
So, if MPE is enabled and the memory fault interrupt is enabled, the first two instructions generate a memory fault and
the corresponding interrupt is executed . To avoid a memory fault under these circumstances, a function must be writ-
ten in flash . This function has to take as an input, the address to be accessed, but it must be passed using a nonpointer
register (such as an accumulator register) . The RAM code routine would write the address into this register (e .g ., A[0]) .