Altera Cyclone V SoC Development Board - Manual (Page 56)

2–48 Chapter 2: Board Components
Memory
Cyclone V SoC Development Board November 2013 Altera Corporation
Reference Manual
Micro SD Flash Memory
The development board supports a micro SD card interface using x4 data lines. This
dedicated HPS interface is the default location for storing HPS boot code, file system,
and FPGA design binaries such as those found in the golden system reference design
file. This 4-bit data interface can sustain burst read operations at up to 50 MHz for a
throughput of 25 MBps.
Table 2–37 lists the micro SD flash memory interface pin assignments, signal names,
and functions. The signal names and types are relative to the Cyclone V SoC in terms
of I/O setting and direction.
I 2 C EEPROM
This board includes a 32 Kb EEPROM device. This device has a 2-wire I 2 C serial
interface bus and is organized as four blocks of 4K x 8-bit memory. This device is
programmed with special board information such as part number, test revision, and
unique MAC addresses for all three Ethernet ports assigned to the board during
manufacturing. This information can be displayed using the Board Test System's GUI
as described in the development kit's user guide. This device can be accessed from the
HPS, FPGA, or MAX V CPLD.
E3 FSM_D9 1.8-V Data bus
F3 FSM_D10 1.8-V Data bus
F4 FSM_D11 1.8-V Data bus
F5 FSM_D12 1.8-V Data bus
H5 FSM_D13 1.8-V Data bus
G7 FSM_D14 1.8-V Data bus
E7 FSM_D15 1.8-V Data bus
Table 2–36. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)
Board
Reference (U6)
Schematic Signal Name I/O Standard Description
Table 2–37. Micro SD Flash Memory Interface Schematic Signal Names and Functions
Board
Reference (J3)
Schematic Signal
Name
Cyclone V SoC
Pin Number
I/O Standard Description
5 SD_CLK A16 3.3-V Clock
7 SD_DAT0 G18 3.3-V Data bus
8 SD_DAT1 C17 3.3-V Data bus
1 SD_DAT2 D17 3.3-V Data bus
2 SD_CD_DAT3 B16 3.3-V Control or data bus
3 SD_CMD F18 3.3-V Control