Altera Cyclone V SoC Development Board User Manual
Page 20
2–12
Chapter 2: Board Components
FPGA Configuration
Cyclone V SoC Development Board
November 2013
Altera Corporation
Reference Manual
illustrates the JTAG chain.
The JTAG chain control DIP switch (SW4) controls the jumpers shown in
To connect a device or interface to the chain, their corresponding switch must be in
the OFF position. Slide all the switches in the ON position to only have the FPGA in
the chain.
1
The MAX V CPLD 5M2210 System Controller must be in the JTAG chain to use some
of the GUI interfaces.
Figure 2–3. JTAG Chain
1
1
1
1
Disable
Trace
TCK
TMS
TDI
TDO
TRST
Cypress On-Board
USB-Blaster II
TCK
TMS
TDI
TDO
10-Pin
JTAG Header
TCK
TMS
TDI
TDO
TRST
Mictor-38
Header
TCK
TMS
TDI
TDO
TRST
Cyclone V SX HPS
TCK
TMS
TDI
TDO
TRST
Cyclone V SX SoC
TCK
TMS
TDI
TDO
HSMC Port A
TCK
TMS
TDI
TDO
5M2210 System
Controller
Flash
Memory
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)