Altera Cyclone V SoC Development Board User Manual
Page 55
Chapter 2: Board Components
2–47
Memory
November 2013
Altera Corporation
Cyclone V SoC Development Board
Reference Manual
F7
FLASH_RDYBSYN
1.8-V
Ready
D4
FLASH_RESETN
1.8-V
Reset
G8
FLASH_WEN
1.8-V
Write enable
C6
FLASH_WPN
1.8-V
Write protect
A1
FSM_A1
1.8-V
Address bus
B1
FSM_A2
1.8-V
Address bus
C1
FSM_A3
1.8-V
Address bus
D1
FSM_A4
1.8-V
Address bus
D2
FSM_A5
1.8-V
Address bus
A2
FSM_A6
1.8-V
Address bus
C2
FSM_A7
1.8-V
Address bus
A3
FSM_A8
1.8-V
Address bus
B3
FSM_A9
1.8-V
Address bus
C3
FSM_A10
1.8-V
Address bus
D3
FSM_A11
1.8-V
Address bus
C4
FSM_A12
1.8-V
Address bus
A5
FSM_A13
1.8-V
Address bus
B5
FSM_A14
1.8-V
Address bus
C5
FSM_A15
1.8-V
Address bus
D7
FSM_A16
1.8-V
Address bus
D8
FSM_A17
1.8-V
Address bus
A7
FSM_A18
1.8-V
Address bus
B7
FSM_A19
1.8-V
Address bus
C7
FSM_A20
1.8-V
Address bus
C8
FSM_A21
1.8-V
Address bus
A8
FSM_A22
1.8-V
Address bus
G1
FSM_A23
1.8-V
Address bus
H8
FSM_A24
1.8-V
Address bus
B6
FSM_A25
1.8-V
Address bus
B8
FSM_A26
1.8-V
Address bus
F2
FSM_D0
1.8-V
Data bus
E2
FSM_D1
1.8-V
Data bus
G3
FSM_D2
1.8-V
Data bus
E4
FSM_D3
1.8-V
Data bus
E5
FSM_D4
1.8-V
Data bus
G5
FSM_D5
1.8-V
Data bus
G6
FSM_D6
1.8-V
Data bus
H7
FSM_D7
1.8-V
Data bus
E1
FSM_D8
1.8-V
Data bus
Table 2–36. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board
Reference (U6)
Schematic Signal Name
I/O Standard
Description