Altera Cyclone V SoC Development Board - Manual (Page 51)

Chapter 2: Board Components 2–43
Memory
November 2013 Altera Corporation Cyclone V SoC Development Board
Reference Manual
R3 DDR3_HPS_A9 G26 1.5-V SSTL Class I Address bus
L7 DDR3_HPS_A10 D29 1.5-V SSTL Class I Address bus
R7 DDR3_HPS_A11 C30 1.5-V SSTL Class I Address bus
N7 DDR3_HPS_A12 B30 1.5-V SSTL Class I Address bus
T3 DDR3_HPS_A13 C29 1.5-V SSTL Class I Address bus
T7 DDR3_HPS_A14 H25 1.5-V SSTL Class I Address bus
M2 DDR3_HPS_BA0 E29 1.5-V SSTL Class I Bank address bus
N8 DDR3_HPS_BA1 J24 1.5-V SSTL Class I Bank address bus
M3 DDR3_HPS_BA2 J23 1.5-V SSTL Class I Bank address bus
K3 DDR3_HPS_CASN E27 1.5-V SSTL Class I Row address select
K9 DDR3_HPS_CKE L29 1.5-V SSTL Class I Column address select
J7 DDR3_HPS_CLK_P L23 1.5-V SSTL Class I Differential output clock
K7 DDR3_HPS_CLK_N M23 1.5-V SSTL Class I Differential output clock
L2 DDR3_HPS_CSN H24 1.5-V SSTL Class I Chip select
E7 DDR3_HPS_DM2 R28 1.5-V SSTL Class I Write mask byte lane
D3 DDR3_HPS_DM3 W30 1.5-V SSTL Class I Write mask byte lane
H3 DDR3_HPS_DQ16 U26 1.5-V SSTL Class I Data bus
G2 DDR3_HPS_DQ17 T26 1.5-V SSTL Class I Data bus
H8 DDR3_HPS_DQ18 N29 1.5-V SSTL Class I Data bus
H7 DDR3_HPS_DQ19 N28 1.5-V SSTL Class I Data bus
F2 DDR3_HPS_DQ20 P26 1.5-V SSTL Class I Data bus
E3 DDR3_HPS_DQ21 P27 1.5-V SSTL Class I Data bus
F8 DDR3_HPS_DQ22 N27 1.5-V SSTL Class I Data bus
F7 DDR3_HPS_DQ23 R29 1.5-V SSTL Class I Data bus
C8 DDR3_HPS_DQ24 P24 1.5-V SSTL Class I Data bus
B8 DDR3_HPS_DQ25 P25 1.5-V SSTL Class I Data bus
A3 DDR3_HPS_DQ26 T29 1.5-V SSTL Class I Data bus
C3 DDR3_HPS_DQ27 T28 1.5-V SSTL Class I Data bus
A7 DDR3_HPS_DQ28 R27 1.5-V SSTL Class I Data bus
D7 DDR3_HPS_DQ29 R26 1.5-V SSTL Class I Data bus
A2 DDR3_HPS_DQ30 V30 1.5-V SSTL Class I Data bus
C2 DDR3_HPS_DQ31 W29 1.5-V SSTL Class I Data bus
G3 DDR3_HPS_DQS_N2 R18
Differential 1.5-V
SSTL Class I
Data strobe P byte lane 0
B7 DDR3_HPS_DQS_N3 R21
Differential 1.5-V
SSTL Class I
Data strobe N byte lane 0
F3 DDR3_HPS_DQS_P2 R19
Differential 1.5-V
SSTL Class I
Data strobe P byte lane 1
C7 DDR3_HPS_DQS_P3 R22
Differential 1.5-V
SSTL Class I
Data strobe N byte lane 1
Table 2–33. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)
Board
Reference
Schematic
Signal Name
Cyclone V SoC
Pin Number
I/O Standard Description