Altera Cyclone V SoC Development Board - Manual (Page 47)

Chapter 2: Board Components 2–39
Memory
November 2013 Altera Corporation Cyclone V SoC Development Board
Reference Manual
L2 DDR3_FPGA_CSN AB15 1.5-V SSTL Class I Chip select
E7 DDR3_FPGA_DM2 AK23 1.5-V SSTL Class I Write mask byte lane
D3 DDR3_FPGA_DM3 AJ27 1.5-V SSTL Class I Write mask byte lane
E3 DDR3_FPGA_DQ16 AE19 1.5-V SSTL Class I Data bus
F2 DDR3_FPGA_DQ17 AE18 1.5-V SSTL Class I Data bus
H8 DDR3_FPGA_DQ18 AG22 1.5-V SSTL Class I Data bus
F8 DDR3_FPGA_DQ19 AK22 1.5-V SSTL Class I Data bus
H3 DDR3_FPGA_DQ20 AF21 1.5-V SSTL Class I Data bus
F7 DDR3_FPGA_DQ21 AF20 1.5-V SSTL Class I Data bus
G2 DDR3_FPGA_DQ22 AH23 1.5-V SSTL Class I Data bus
H7 DDR3_FPGA_DQ23 AK24 1.5-V SSTL Class I Data bus
D7 DDR3_FPGA_DQ24 AF24 1.5-V SSTL Class I Data bus
C8 DDR3_FPGA_DQ25 AF23 1.5-V SSTL Class I Data bus
C3 DDR3_FPGA_DQ26 AJ24 1.5-V SSTL Class I Data bus
C2 DDR3_FPGA_DQ27 AK26 1.5-V SSTL Class I Data bus
B8 DDR3_FPGA_DQ28 AE23 1.5-V SSTL Class I Data bus
A7 DDR3_FPGA_DQ29 AE22 1.5-V SSTL Class I Data bus
A2 DDR3_FPGA_DQ30 AG25 1.5-V SSTL Class I Data bus
A3 DDR3_FPGA_DQ31 AK27 1.5-V SSTL Class I Data bus
F3 DDR3_FPGA_DQS_P2 Y17
Differential 1.5-V
SSTL Class I
Data strobe P byte lane 2
G3 DDR3_FPGA_DQS_N2 AA18
Differential 1.5-V
SSTL Class I
Data strobe N byte lane 2
C7 DDR3_FPGA_DQS_P3 AC20
Differential 1.5-V
SSTL Class I
Data strobe P byte lane 3
B7 DDR3_FPGA_DQS_N3 AD19
Differential 1.5-V
SSTL Class I
Data strobe N byte lane 3
K1 DDR3_FPGA_ODT AE16 1.5-V SSTL Class I On-die termination enable
J3 DDR3_FPGA_RASN AH8 1.5-V SSTL Class I Row address select
T2 DDR3_FPGA_RESETN AK21 1.5-V SSTL Class I Reset
L3 DDR3_FPGA_WEN AJ6 1.5-V SSTL Class I Write enable
L8 DDR3_FPGA_ZQ01 — 1.5-V SSTL Class I ZQ impedance calibration
DDR3 x16 (U38)
N3 DDR3_FPGA_A0 AJ14 1.5-V SSTL Class I Address bus
P7 DDR3_FPGA_A1 AK14 1.5-V SSTL Class I Address bus
P3 DDR3_FPGA_A2 AH12 1.5-V SSTL Class I Address bus
N2 DDR3_FPGA_A3 AJ12 1.5-V SSTL Class I Address bus
P8 DDR3_FPGA_A4 AG15 1.5-V SSTL Class I Address bus
P2 DDR3_FPGA_A5 AH15 1.5-V SSTL Class I Address bus
Table 2–32. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board
Reference
Schematic
Signal Name
Cyclone V SoC
Pin Number
I/O Standard Description