Altera Cyclone V SoC Development Board - Manual (Page 44)

2–36 Chapter 2: Board Components
Components and Interfaces
Cyclone V SoC Development Board November 2013 Altera Corporation
Reference Manual
SDI Video
The serial digital interface (SDI) video port consists of a LMH0303 cable driver
(output) and a LMH0384 cable equalizer (input). The PHY devices from National
Semiconductor interface to single-ended 75-
Ω SMB connectors.
SDI Video Output
The cable driver supports operation at 270 Mb standard definition (SD), 1.5 Gb high
definition (HD), and 3.0 Gb dual-link HD modes. The data rate is driven directly from
the Cyclone V SoC transceiver output using a slower-speed CMU channel (maximum
of 3.125 Gbps). The device can be clocked by the 148.5 MHz voltage-controlled crystal
oscillator (VCXO) and matched to incoming signals within 50 ppm using the UP and
DN voltage control lines to the VCXO.
Table 2–28 shows the supported output standards for the SD and HD input.
f
For more information about the application circuit of the LMH0303 cable driver, refer
to the cable driver data sheet at
www.national.com .
Table 2–29 summarizes the SDI video output interface pin assignments, signal names,
and functions.
0x5B HPS power monitor
0x5E FPGA and HPS power monitor synchronize
0x51 EEPROM
0x70 Si5356 quad-programmable clock
0x66 Si570 programmable oscillator
0x55 Si571 programmable oscillator
Table 2–27. I 2 C interface address map
Address Device
Table 2–28. Supported Output Standards for SD and HD Input
SD_HD Input Supported Output Standards Rise TIme
0 SMPTE 424M, SMPTE 292M Faster
1 SMPTE 259M Slower
Table 2–29. SDI Video Output Interface Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (U25)
Schematic Signal Name I/O Standard
Cyclone V SoC Device
Pin Number
Description
6 SDI_TX_EN 2.5-V AA30 Device enable
4 SDI_TX_RSET 3.3-V — Device reset
10 SDI_TX_SD_HDn 2.5-V AC29 Slew rate control
1 SDI_TX_P 1.5-V PCML T4 SDI video input P
2 SDI_TX_N 1.5-V PCML T3 SDI video input N