Altera Cyclone V SoC Development Board - Manual (Page 49)

Chapter 2: Board Components 2–41
Memory
November 2013 Altera Corporation Cyclone V SoC Development Board
Reference Manual
DDR3 SDRAM (HPS)
The development board supports three 32Mx16x8 banks DDR3 SDRAM interface for
very high-speed sequential memory access. The 40-bit data bus comprises of three ×16
devices with a single address or command bus. This interface connects to the
dedicated HMC for HPS I/O banks on the top edge of the FPGA.
The DDR3 device shipped with this board are running at 400 MHz, for a total
theoretical bandwidth of over 25.6 Gbps. The speed grade of this DDR3 device is
800 MHz with a CAS latency of 9.
Table 2–32 lists the DDR3 SDRAM pin assignments, signal names, and functions. The
signal names and types are relative to the Cyclone V SoC in terms of I/O setting and
direction.
C7 DDR3_FPGA_DQS_P1 V17
Differential 1.5-V
SSTL Class I
Data strobe P byte lane 1
B7 DDR3_FPGA_DQS_N1 W17
Differential 1.5-V
SSTL Class I
Data strobe N byte lane 1
K1 DDR3_FPGA_ODT AE16 1.5-V SSTL Class I On-die termination enable
J3 DDR3_FPGA_RASN AH8 1.5-V SSTL Class I Row address select
T2 DDR3_FPGA_RESETN AK21 1.5-V SSTL Class I Reset
L3 DDR3_FPGA_WEN — 1.5-V SSTL Class I Write enable
L8 DDR3_FPGA_ZQ01 — 1.5-V SSTL Class I ZQ impedance calibration
Table 2–32. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Board
Reference
Schematic
Signal Name
Cyclone V SoC
Pin Number
I/O Standard Description
Table 2–33. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 5)
Board
Reference
Schematic
Signal Name
Cyclone V SoC
Pin Number
I/O Standard Description
DDR3 x16 (U30)
N3 DDR3_HPS_A0 F26 1.5-V SSTL Class I Address bus
P7 DDR3_HPS_A1 G30 1.5-V SSTL Class I Address bus
P3 DDR3_HPS_A2 F28 1.5-V SSTL Class I Address bus
N2 DDR3_HPS_A3 F30 1.5-V SSTL Class I Address bus
P8 DDR3_HPS_A4 J25 1.5-V SSTL Class I Address bus
P2 DDR3_HPS_A5 J27 1.5-V SSTL Class I Address bus
R8 DDR3_HPS_A6 F29 1.5-V SSTL Class I Address bus
R2 DDR3_HPS_A7 E28 1.5-V SSTL Class I Address bus
T8 DDR3_HPS_A8 H27 1.5-V SSTL Class I Address bus
R3 DDR3_HPS_A9 G26 1.5-V SSTL Class I Address bus
L7 DDR3_HPS_A10 D29 1.5-V SSTL Class I Address bus
R7 DDR3_HPS_A11 C30 1.5-V SSTL Class I Address bus
N7 DDR3_HPS_A12 B30 1.5-V SSTL Class I Address bus
T3 DDR3_HPS_A13 C29 1.5-V SSTL Class I Address bus