Altera Cyclone V SoC Development Board - Manual (Page 19)

Chapter 2: Board Components 2–11
FPGA Configuration
November 2013 Altera Corporation Cyclone V SoC Development Board
Reference Manual
FPGA Configuration
This section describes the FPGA, flash memory, and MAX V CPLD 5M2210 System
Controller device programming methods supported by the Cyclone V SoC
development board.
The Cyclone V SoC development board supports the following configuration
methods:
■ JTAG
■ Embedded USB-Blaster II is the default method for configuring the FPGA
using the Quartus II Programmer in JTAG mode with the supplied USB cable.
■ External Mictor connector for configuring the HPS using the ARM DS-5 Altera
Edition software and DSTREAM or Lauterbach cables.
■ External USB-Blaster for configuring the FPGA when you connect the external
USB-Blaster to the JTAG header (J23).
■ Flash memory download for configuring the FPGA using stored images from the
flash memory on either power-up or pressing the configure push button (S12).
■ EPCQ device for FPGA configuration in Active Serial (AS) mode on power-up.
FPGA Programming over Embedded USB-Blaster II
This configuration method implements a mini-USB connector (J37), a USB 2.0 PHY
device (U51), and an Altera MAX II CPLD EPM570GF100I5N (U47) to allow FPGA
configuration using a USB cable. This USB cable connects directly between the USB
connector on the board and a USB port on a PC running the Quartus II software.
The embedded USB-Blaster II in the MAX II CPLD EPM570GF100I5N normally
masters the JTAG chain. The embedded USB-Blaster II shares the pins with the
external header. The embedded USB-Blaster II is automatically disabled when you
connect an external USB-Blaster to the JTAG chain through the JTAG header (J23). In
addition to JTAG interface, the embedded USB-Blaster II have trace capabilities for
HPS debug purposes. The trace interface from the HPS routes to the embedded
USB-Blaster II connection pins through the FPGA.