Altera Cyclone V SoC Development Board - Manual (Page 48)

2–40 Chapter 2: Board Components
Memory
Cyclone V SoC Development Board November 2013 Altera Corporation
Reference Manual
R8 DDR3_FPGA_A6 AK12 1.5-V SSTL Class I Address bus
R2 DDR3_FPGA_A7 AK13 1.5-V SSTL Class I Address bus
T8 DDR3_FPGA_A8 AH13 1.5-V SSTL Class I Address bus
R3 DDR3_FPGA_A9 AH14 1.5-V SSTL Class I Address bus
L7 DDR3_FPGA_A10 AJ9 1.5-V SSTL Class I Address bus
R7 DDR3_FPGA_A11 AK9 1.5-V SSTL Class I Address bus
N7 DDR3_FPGA_A12 AK7 1.5-V SSTL Class I Address bus
T3 DDR3_FPGA_A13 AK8 1.5-V SSTL Class I Address bus
T7 DDR3_FPGA_A14 AG12 1.5-V SSTL Class I Address bus
M2 DDR3_FPGA_BA0 AH10 1.5-V SSTL Class I Bank address bus
N8 DDR3_FPGA_BA1 AJ11 1.5-V SSTL Class I Bank address bus
M3 DDR3_FPGA_BA2 AK11 1.5-V SSTL Class I Bank address bus
K3 DDR3_FPGA_CASN AH7 1.5-V SSTL Class I Row address select
K9 DDR3_FPGA_CKE AJ21 1.5-V SSTL Class I Column address select
J7 DDR3_FPGA_CLK_P AA15 1.5-V SSTL Class I Differential output clock
K7 DDR3_FPGA_CLK_N AA14 1.5-V SSTL Class I Differential output clock
L2 DDR3_FPGA_CSN AB15 1.5-V SSTL Class I Chip select
E7 DDR3_FPGA_DM0 AH17 1.5-V SSTL Class I Write mask byte lane
D3 DDR3_FPGA_DM1 AG23 1.5-V SSTL Class I Write mask byte lane
E3 DDR3_FPGA_DQ0 AF18 1.5-V SSTL Class I Data bus
F2 DDR3_FPGA_DQ1 AE17 1.5-V SSTL Class I Data bus
H8 DDR3_FPGA_DQ2 AG16 1.5-V SSTL Class I Data bus
F8 DDR3_FPGA_DQ3 AF16 1.5-V SSTL Class I Data bus
H3 DDR3_FPGA_DQ4 AH20 1.5-V SSTL Class I Data bus
F7 DDR3_FPGA_DQ5 AG21 1.5-V SSTL Class I Data bus
G2 DDR3_FPGA_DQ6 AJ16 1.5-V SSTL Class I Data bus
H7 DDR3_FPGA_DQ7 AH18 1.5-V SSTL Class I Data bus
D7 DDR3_FPGA_DQ8 AK18 1.5-V SSTL Class I Data bus
C8 DDR3_FPGA_DQ9 AJ17 1.5-V SSTL Class I Data bus
C3 DDR3_FPGA_DQ10 AG18 1.5-V SSTL Class I Data bus
C2 DDR3_FPGA_DQ11 AK19 1.5-V SSTL Class I Data bus
B8 DDR3_FPGA_DQ12 AG20 1.5-V SSTL Class I Data bus
A7 DDR3_FPGA_DQ13 AF19 1.5-V SSTL Class I Data bus
A2 DDR3_FPGA_DQ14 AJ20 1.5-V SSTL Class I Data bus
A3 DDR3_FPGA_DQ15 AH24 1.5-V SSTL Class I Data bus
F3 DDR3_FPGA_DQS_P0 V16
Differential 1.5-V
SSTL Class I
Data strobe P byte lane 0
G3 DDR3_FPGA_DQS_N0 W16
Differential 1.5-V
SSTL Class I
Data strobe N byte lane 0
Table 2–32. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board
Reference
Schematic
Signal Name
Cyclone V SoC
Pin Number
I/O Standard Description