Altera Cyclone V SoC Development Board - Manual (Page 11)

Chapter 2: Board Components 2–3
Board Overview
November 2013 Altera Corporation Cyclone V SoC Development Board
Reference Manual
SW3 MSEL DIP switch
Controls the configuration scheme on the board. MSEL pins 0, 1, 2 and
4 connects to the DIP switch while MSEL pin 3 connects to ground.
S11 Program select push button
Toggles the program select LEDs, which selects the program image
that loads from flash memory to the FPGA.
S12 Configure push button
Load image from flash memory to the FPGA based on the settings of
the program select LEDs.
D37 Configuration done LED Illuminates when the FPGA is configured.
D34 Load LED
Illuminates when the MAX V CPLD 5M2210 System Controller is
actively configuring the FPGA.
D36 Error LED Illuminates when the FPGA configuration from flash memory fails.
D35 Power LED Illuminates when 5.0-V power is present.
D30, D31 JTAG TX/RX LEDs
Indicate the transmit or receive activity of the JTAG chain. The TX and
RX LEDs would flicker if the link is in use and active. The LEDs are
either off when not in use or on when in use but idle.
D39–D41 Program select LEDs
Illuminates to show which flash memory image loads to the FPGA
when you press the program select push button. Refer to
Table 2–6 for
the LED settings.
D9 HSMC port present LED Illuminates when a daughter card is plugged into the HSMC port.
D14, D15 UART LEDs Illuminates when UART transmitter and receiver are in use.
Clock Circuitry
X1 Programmable oscillator
Programmable oscillator with a default frequency of 100 MHz. The
frequency is programmable using the clock control GUI running on the
MAX V CPLD 5M2210 System Controller.
X4 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic.
X3 148.5-MHz oscillator
Programmable voltage-controlled crystal oscillator (VCXO) with a
default frequency of 148.5 MHz. The frequency is programmable using
the clock control GUI running on the MAX V CPLD 5M2210 System
Controller.
J36 Clock input SMA connector Drive CMOS-compatible clock inputs into the clock multiplexer buffer.
U29 Multi-output oscillator
Si5338C quad-output programmable oscillator with 100M, 25M, 25M,
and 156.25M outputs.
U35 Multi-output oscillator
Si5338C quad-output fixed oscillator with 25M, 25M, 100M, and 100M
outputs.
General User Input/Output
D1–D8 User LEDs Eight user LEDs. Illuminates when driven low.
SW1 User DIP switch User DIP switch. When the switch is ON, a logic 0 is selected.
S10 CPU reset push button Reset the FPGA logic.
S2 MAX V reset push button Reset the MAX V CPLD 5M2210 System Controller.
S1–S6 General user push buttons Six user push buttons. Driven low when pressed.
Memory Devices
U37, U38, U30,
U22, U14
DDR3 memory
Two 4-Gbit DDR3 SDRAM with a 16-bit data bus for the FPGA and
three 4-Gbit DDR3 SDRAM with a 16-bit data bus for the HPS.
U5 QSPI flash 1-Gb serial NOR flash with 4-bit data bus.
Table 2–1. Board Components (Part 2 of 3)
Board Reference Type Description