Altera JESD204B IP - Manual (Page 51)

For the alignment of LMFC to the TX logic, the JESD204 TX IP core samples SYNC_N from the DAC
receiver and reports the relative phase difference between the DAC and TX logic device LMFC in the TX
CSR (
dbg_phadj
,
dbg_adjdir
, and
dbg_adjcnt
). Based on the reported value, you can calculate the
adjustment required. Then, to initiate the link reinitialization through the CSR, set the value in the TX
CSR (
csr_phadj
,
csr_adjdir
, and
csr_adjcnt
). The values on the phase adjustment are embedded in
bytes 1 and 2 of the ILAS sequence that is sent to the DAC during link initialization. On the reception of
the ILAS, the DAC adjusts its LMFC phase by step count value and sends back an error report with the
new LMFC phase information. This process may be repeated until the LMFC at the DAC and the logic
device are aligned.
Scrambler/Descrambler
Both the scrambler and descrambler are designed in a 32-bit parallel implementation and the scrambling/
descrambling order starts from first octet with MSB first.
The JESD204 TX and RX IP core support scrambling by implementing a 32-bit parallel scrambler in each
lane. The scrambler and descrambler are located in the JESD204 IP MAC interfacing to the Avalon-ST
interface. You can enable or disable scrambling and this option applies to all lanes. Mixed mode
operation, where scrambling is enabled for some lanes, is not permitted.
The scrambling polynomial:
1 + x
14 + x 15
The descrambler can self-synchronize in eight octets. In a typical application where the reset value of the
scrambler seed is different from the converter device to FPGA logic device, the correct user data is
recovered in the receiver in two link clocks (due to the 32-bit architecture). The PRBS pattern checker on
the transport layer should always disable checking of the first eight octets from the JESD204 RX IP core.
SYNC_N Signal
For Subclass 0 implementation, the
SYNC_N
signal from the DAC converters in the same group path must
be combined.
In some applications, multiple converters are grouped together in the same group path to sample a signal
(referred as multipoint link). The FPGA can only start the LMFC counter and its transition to ILAS after
all the links deassert the synchronization request. The JESD204B TX IP core provides three signals to
facilitate this application. The
SYNC_N
is the direct signal from the DAC converters. The error signaling
from
SYNC_N
is filtered and sent out as
dev_sync_n
signal. For Subclass 0, you need to multiplex all the
dev_sync_n
signals in the same multipoint link and then input them to the IP core through
mdev_sync_n
signal.
4-14 Scrambler/Descrambler
UG-01142
2015.05.04
Altera Corporation JESD204B IP Core Functional Description
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