Altera JESD204B IP - Manual (Page 25)

Programming an FPGA Device
After successfully compiling your design, program the targeted Altera device with the Quartus II
Programmer and verify the design in hardware. For instructions on programming the FPGA device, refer
to the Device Programming section in volume 3 of the Quartus II Handbook.
Related Information
Device Programming
JESD204B IP Core Design Considerations
You must be aware of the following conditions when integrating the JESD204B IP core in your design:
• Intergrating the IP core in Qsys
• Pin assignments
• Adding external transceiver PLL
• Timing constraints for the input clock
Integrating the JESD204B IP core in Qsys
You can integrate the JESD204B IP core with other Qsys components within Qsys.
You can connect standard interfaces like clock, reset, Avalon-MM, Avalon-ST, HSSI bonded clock, HSSI
serial clock, and interrupt interfaces within Qsys. However, for conduit interfaces, you are advised to
export all those interfaces and handle them outside of Qsys. (9) This is because conduit interfaces are not
part of the standard interfaces. Thus, there is no guarantee on compatibility between different conduit
interfaces.
Note: The Transport Layer provided in this JESD204B IP core design example is not supported in Qsys.
Therefore, you must export all interfaces that connect to the Transport Layer (for example,
jesd204_tx_link interface) and connect them to a transport layer outside of Qsys.
(9) You can also connect conduit interfaces within Qsys but you must create adapter components to handle all
the incompatibility issues like incompatible signal type and width.
UG-01142
2015.05.04
Programming an FPGA Device 3-11
Getting Started Altera Corporation
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