Altera JESD204B IP User Manual
Page 29
Table 3-4: Example A
Original clock
names in altera_
jesd204.sdc
User design input
clock names
Frequency
(MHz)
Recommended SDC timing constraint
tx_pll_ref_clk
xcvr_tx_rx_refclk 250
create_clock -name xcvr_tx_rx_refclk -period 4.0
[get_ports xcvr_tx_rx_refclk ]
create_clock -name device_clk -period 8.0 [get_ports
device_clk]
create_clock -name jesd204_avs_clk -period 10.0
[get_ports jesd204_avs_clk]
create_clock -name phy_mgmt_clk -period 13.3 [get_
ports phy_mgmt_clk]
derive_pll_clocks
set_clock_groups -asynchronous \
-group {xcvr_tx_rx_refclk \
report_clock commands> \
} \
-group {device_clk \
report_clock commands> \
} \
-group {jesd204_avs_clk} \
-group {phy_mgmt_clk \
report_clock commands> \
}
rx_pll_ref_clk
txlink_clk
device_clk
125
rxlink_clk
tx_avs_clk
jesd204_avs_clk
100
rx_avs_clk
reconfig_clk
(10)
phy_mgmt_clk
75
However, if your design requires you to connect the
rx_avs_clk
and
reconfig_clk
to the same clock,
you need to put them in the same clock group.
The table below shows an example where the
device_clk
in this design is an input into the transceiver
refclk
pin. The IP core's Avalon-MM interface shares the same clock source as the transceiver
management clock.
(10)
For Arria 10 device only.
UG-01142
2015.05.04
Timing Constraints For Input Clocks
3-15
Getting Started
Altera Corporation