Altera JESD204B IP - Manual (Page 24)

Table 3-3: Simulation Run Scripts
Simulator File Directory Script
ModelSim-Altera
SE/AE
/ip_sim/testbench/mentor run_altera_jesd204_tb.tcl
VCS /ip_sim/testbench/synopsys/vcs run_altera_jesd204_tb.sh
VCS MX /ip_sim/testbench/synopsys/
vcsmx
run_altera_jesd204_tb.sh
Aldec Riviera /ip_sim/testbench/aldec run_altera_jesd204_tb.tcl
Cadence /ip_sim/testbench/cadence run_altera_jesd204_tb.sh
To simulate the testbench design using the ModelSim-Altera or Aldec Riviera-PRO simulator, follow
these steps:
1. Launch the ModelSim-Altera or Aldec Riviera-PRO simulator.
2. On the File menu, click Change Directory > Select <example_design_directory>/ip_sim/testbench/
<simulator name>.
3. On the File menu, click Load > Macro file. Select run_altera_jes204_tb.tcl. This file compiles the
design and runs the simulation automatically, providing a pass/fail indication on completion.
To simulate the testbench design using the VCS, VCS MX (in Linux), or Cadence simulator, follow these
steps:
1. Launch the VCS, VCS MX, or Cadence simulator.
2. On the File menu, click Change Directory > Select <example_design_directory>/ip_sim/testbench/
<simulator name>.
3. Run the run_altera_jes204_tb.sh file. This file compiles the design and runs the simulation automati‐
cally, providing a pass/fail indication on completion.
Related Information
Simulating Altera Designs
More information about Altera simulation models.
Compiling the JESD204B IP Core Design
Before you begin
Refer to the JESD204B IP Core Design Considerations on page 3-11 before compiling the JESD204B
IP core design.
To compile your design, click Start Compilation on the Processing menu in the Quartus II software. You
can use the generated .qip file to include relevant files into your project.
Related Information
• JESD204B IP Core Design Considerations on page 3-11
• Quartus II Help
More information about compilation in Quartus II software.
3-10 Compiling the JESD204B IP Core Design
UG-01142
2015.05.04
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