Altera JESD204B IP User Manual
Page 128
Signal
Clock
Domain
Direction
Description
avst_usr_
din[(FRAMECLK_
DIV*LINK*M*S*N)-1:0]
frame_
clk
Input
TX data from the Avalon-ST source interface. The
source arranges the data in a specific order, as
illustrated in the cases below:
Case 1: If F1/F2_FRAMECLK_DIV =1, LINK = 1, M
= 1, S =1, N = 16:
• avst_usr_din[15:0]
Case 2: If F1/F2_FRAMECLK_DIV =1, LINK = 1, M
= 2 (denoted by m0 and m1), S =1, N = 16:
• avst_usr_din[15:0] = m0[15:0]
• avst_usr_din[31:16] = m1[15:0]
Case 3: If F1/F2_FRAMECLK_DIV =1, LINK = 2
(denoted by link0 and link1), M = 1, S =1, N = 16:
• avst_usr_din[15:0] = link0
• avst_usr_din[31:16] = link1
Case 4: If F1/F2_FRAMECLK_DIV =1, LINK = 2
(denoted by link0 and link1), M = 2 (denoted by m0
and m1), S =1, N = 16:
• avst_usr_din[15:0] = link0, m0[15:0]
• avst_usr_din[31:16] = link0, m1[15:0]
• avst_usr_din[47:32] = link1, m0[15:0]
• avst_usr_din[63:48] = link1, m1[15:0]
avst_usr_din_valid
frame_
clk
Input
Indicates whether the data from the Avalon-ST
source interface to the transport layer is valid or
invalid.
• 0—data is invalid
• 1—data is valid
avst_usr_din_ready
frame_
clk
Output
Indicates that the transport layer is ready to accept
data from the Avalon-ST source interface.
• 0—transport layer is not ready to receive data
• 1—transport layer is ready to receive data
UG-01142
2015.05.04
System Interface Signals
5-47
JESD204B IP Core Design Guidelines
Altera Corporation