Generating and simulating the design example, Generating the design example simulation model, Generating and simulating the design example -55 – Altera JESD204B IP User Manual

Page 136: Ip core design example for simulation—refer to

.
.
11 : 1111111111111111; -- End of MIF
[12..15] : 0000000000000000;
END;

ADC/DAC/CLK

The content for ADC/DAC/CLK MIF is vendor-specific. The general format for the MIF is as shown

below, with each section terminated by all 1's.

Maximum Configuration MIF
WIDTH=32;
DEPTH=128;

ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;

CONTENT BEGIN
0 : 10000100000000000001000001111100; -- (Maximum Config)
1 : 10000100000000000001010000000101;
2 : 10000100000000000001011000000101;
3 : 10000100000000000001110000000010;
.
.
.
28 : 10000001000000001111111100000001;
29 : 10000001000000000101111100010100;
30 : 11111111111111111111111111111111; -- End of MIF
[31..63] : 00000000000000000000000000000000;

Downscale Configuration MIF

64 : 10000100000000000001000001111100; -- (downscale config)
65 : 10000100000000000001010000000101;
66 : 10000100000000000001011000000101;
67 : 10000100000000000001110000000010;
.
.
.
92 : 10000001000000001111111100000001;
93 : 10000001000000000101111100010100;
94 : 11111111111111111111111111111111; -- End of MIF
95..127] : 00000000000000000000000000000000;
END;

Generating and Simulating the Design Example

To use the JESD204B IP core design example testbench, follow these steps:
1. Generate the design example simulation testbench. Refer to

Generating the Design Example

Simulation Model

on page 5-55

2. Simulate the design example using simulator-specific scripts. Refer to

Simulating the JESD204B IP

Core Design Example

on page 5-56

Generating the Design Example Simulation Model

After generating the IP core, generate the design example simulation testbench using the script

(gen_ed_sim_verilog.tcl or gen_ed_sim_vhdl) located in the <example_design_directory>