Altera JESD204B IP User Manual
Page 123
Mode
Link
L
M
F
Reference
Clock
Frame
Clock
Link
Clock
F1_
FRAMECLK_
DIV
F2_
FRAMECLK_
DIV
Bonded/Non-bonded
1
8
1
1
307.2
153.6
153.6
4
Bonded/Non-bonded
1
8
2
1
307.2
153.6
153.6
4
Bonded/Non-bonded
1
8
4
1
307.2
153.6
153.6
4
Bonded/Non-bonded
1
8
4
2
307.2
153.6
153.6
2
Dynamic Reconfiguration
Non-bonded
2
2
2
2
153.6
153.6
153.6
2
The following figures show the datapath of single and multiple JESD204B links.
Figure 5-17: Datapath of A Single JESD204B Link
Pattern Generator
M = 1, S = 1, N = 16,
FRAMECLK_DIV = 1
Pattern Checker
Assembler
LMF = 211, S = 1,
N = 16
Deassembler
LMF = 211, S = 1,
N = 16
TX Base Core
LMF = 211, S = 1,
N = 16
RX Base Core
LMF = 211, S = 1,
N = 16
Duplex
SERDES
PHY
32
32
16
16
Avalon-ST
Avalon-ST
Avalon-ST
Avalon-ST
Transport Layer 0
JESD204B IP Duplex Core 0 (LMF = 211)
LINK 0
M = 1, S = 1, N = 16,
FRAMECLK_DIV = 1
5-42
System Parameters
UG-01142
2015.05.04
Altera Corporation
JESD204B IP Core Design Guidelines
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