Altera JESD204B IP User Manual
Page 39
Figure 4-1: Overview of the JESD204B IP Core Block Diagram
RX
Driver
TX
Driver
Deserializer
Serializer
Frame/Lane
Alignment
Character
Generation
Descrambler
Scrambler
Data Frame
Assembly
Data Frame
Deassembly
SYSREF
Frame Clock
ADC Application
Layer
DAC Application
Layer
Transport Layer
Data Link Layer
Physical Layer
Word
Aligner
Soft Logic
Hard Logic
JESD204B IP Core
JESD204B
Design Example
jesd204_tx_top
MAC (jesd204_tx_base)
MAC (jesd204_rx_base)
PHY (jesd204_rx_phy)
PHY (jesd204_tx_phy)
jesd204_rx_top
8B/10B
Encoder
8B/10B
Decoder
SYNC~
SYNC~
Frame/Lane
Alignment
Character Buffer/
Replace/
Monitor
4-2
JESD204B IP Core Functional Description
UG-01142
2015.05.04
Altera Corporation
JESD204B IP Core Functional Description
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