Tx latency, Rx path – Altera JESD204B IP User Manual
Page 105
Figure 5-8: TX Error Reporting
The
jesd204_tx_data_valid
signal deasserts for one frame_clk and cannot be sampled by the link_clk.
txframe_clk
txlink_clk
jesd204_tx_data_valid
jesd204_tx_data_ready
jesd204_tx_link_data_valid
jesd204_tx_link_error
TX Latency
Table 5-10: TX Latency Associated with Different F and FRAMECLK_DIV Settings.
F
FRAMECLK_DIV
TX Latency
1
1
3
txframe_clk
period.
• Maximum 5
txframe_clk
period for byte 3
• Minimum 2
txframe_clk
period for byte 0
1
4
1
txframe_clk
period
2
1
3
txframe_clk
period.
• Maximum 4
txframe_clk
period for byte 2 and byte 3
• Minimum 3
txframe_clk
period for byte 0 and byte 1
2
2
1
txframe_clk
period
4
—
1
txframe_clk
period
8
—
1
txframe_clk
period
RX Path
The deassembler in the RX path consists of the tail bits dropping, deassembling, and multiplexing blocks.
5-24
TX Latency
UG-01142
2015.05.04
Altera Corporation
JESD204B IP Core Design Guidelines
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