Altera JESD204B IP User Manual
Page 135
27 : 3FFFFFF; -- End of MIF
END;
xcvr_cdr_combined.mif
Maximum Configuration MIF
CONTENT BEGIN
00 : 006DF02; -- Start of MIF
01 : 007FF09;
02 : 008FF04;
03 : 00AFF01;
.
.
.
76 : 173FF31;
77 : 1741F0C;
78 : 1753F13;
79 : 3FFFFFF; -- End of MIF
Downscale Channel Configuration MIF
7A : 006DF02; -- Start of MIF
7B : 007FF09;
7C : 008FF04;
7D : 00AFF01;
.
.
.
F0 : 173FF31;
F1 : 1741F0C;
F2 : 1753F13;
F3 : 3FFFFFF; -- End of MIF
END;
JESD
The current JESD MIF contains only the LMF information. You need to manually code the MIF content
in the following format.
Maximum Configuration MIF
WIDTH=16;
DEPTH=16;
ADDRESS_RADIX=UNS;
DATA_RADIX=BIN;
CONTENT BEGIN
0 : 0000000000000001; -- L (maximum config)
1 : 0000000000000001; -- M
2 : 0000000000000001; -- F
.
.
.
3 : 1111111111111111; -- End of MIF
[4..7] : 0000000000000000;
Downscale Configuration MIF
8 : 0000000000000000; -- L (downscale config)
9 : 0000000000000000; -- M
10 : 0000000000000001; -- F
.
5-54
MIF ROM
UG-01142
2015.05.04
Altera Corporation
JESD204B IP Core Design Guidelines
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)