Echelon FTXL - Manual (Page 232)

220 Example FTXL Applications
e. Select Program FPGA configuration data into hardware-image
region of flash memory to load the hardware design into flash
along with the software design.
If necessary, specify the following information for the FPGA
configuration:
i. Click Browse next to the FPGA Configuration (SOF)
dropdown list box to select the DBC2C20_FTXL.sof
hardware design file from the
[ Altera ]\nios2eds\examples\vhdl\DBC2C20_FTXL\Stan
dard directory.
ii. Select Nios II EP2C35 epcs from the Hardware Image
dropdown list box.
iii. Select epcs_controller from the Memory dropdown list
box.
iv. Enter 0x0 in the Offset field.
f. Select Validate Nios II system ID before software download.
g. Click Apply to save the named configuration.
h. Click Program Flash to load the software image into the Nios II
processor. Loading the software image can take a few moments.
i. If the Program Flash Now? dialog appears, click Yes.
6. After the software is loaded, perform a reset by disconnecting power from
the DBC2C20 development board and reconnecting power to the board.
7. Close the Quartus II Programmer window. You can also close the Nios II
IDE window.
The Nios II processor runs the loaded software as soon as the processor completes
restart processing.
Running the Example Applications
If you loaded the application image into the Nios II processor, the application
runs automatically as soon as the Nios II processor is properly programmed and
reset.
You can also run the application from the Nios II EDS IDE:
1. Ensure that the DBC2C20 development board is powered on and that the
USB-Blaster download cable is connected to the JTAG header connector
(P1).
2. Start the Nios II EDS IDE.
3. Ensure that the workspace includes the example application project that
you want to run.
4. Right-click the appropriate project (either FTXL_Simple_0 or
FTXL_Dynamic_Interface_0) from the Nios II C/C++ Projects pane and
select Run As → Nios II Hardware. The Nios II EDS IDE recompiles the
project.