ADLINK PCIe-7360 - Manual (Page 76)

66 Operations
SPI master of PCIe-7360 provide at most 64 bits -- 32 bits
address/ command and 32 bits data. SPI master of PCIe-7360
supports only one slave device. Figure 3-32 shows the data trans-
fer on SPI bus.
Figure 3-33: Data Transfer on SPI Bus
SPI master of PCIe-7360 supports clock frequency range from
244.14 kHz to 62.5 MHz. After issuing command to SPI slave
device, the clock rate might be changed according the request
from SPI slave. The below formula is to calculate the SPI clock
rate.
Fscl = 62.5 / (Clk Pre-scale + 1) (MHz),
where Clk Pre-scale=0 to 255
SPI master of PCIe-7360 supports two different modes of SCK.
Clock modes 0 and 1 of SCK are as shown.
Figure 3-34: Clock Mode of SCK
CS#
SCK
Data
Data
SDO
SDI
Cmd/Addr
Cmd/Addr 0 ~ 32b
RD 0 ~ 32b
TD 0 ~ 32b dummy dummy
dummy