ADLINK PCIe-7360 - Manual (Page 16)

6 Introduction
1.3.5 Timing Accuracy
Acquisition Timing
Channel-to-Cannel skew ±1.08 ns
Setup time to sampled clock (t
SU
) 2 ns
Hold time to sampled clock (t
H
) 2 ns
Time delay of external sampled clock from AFI7 to
internal (t
AF7D
)
6.3 ns
Time delay of external sampled clock from SMB CLK
in to internal (t
SMBID
)
9.1 ns
Time delay of DI data from VHDCI connector to
internal (t
DID
)
3.26 ns - 4.34 ns
Generation Timing
Exported clock skew AFI6 -to- SMB CLK out
(t
ECskew
)
2 ns
Exported clock (AFI6) -to- DO data delay (t
AF62D
) 600 ps - 5 ns