4 sample clock phase shift, Sample clock phase shift, See figure 3-4 – ADLINK PCIe-7360 User Manual

Page 37: See figure 3-5

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Operations

PCIe-7360

Figure 3-4: DI raw data Mapping for 24-Bit Data Width

Figure 3-5: DI raw data Mapping for 32-Bit Data Width

3.4 Sample Clock Phase Shift

PCIe-7360 features phase shift of sample clock (on SMB connec-
tor or AFI6 & AFI7 of SCSI-VHDCI connector). The sample clock
can be from external DUT or can be the exporting clock generated
from internal time base. The resolution of phase shift is 80 step,
implemented by Phase-Locked Loop (PLL) function of FPGA. In