ADLINK PCIe-7360 - Manual (Page 7)

List of Figures vii
PCIe-7360
List of Figures
Figure 1-1: Acquisition Timing Diagram ............................................. 7
Figure 1-2: Generation Timing Diagram............................................. 8
Figure 1-3: PCIe-7360 Schematic Diagram ..................................... 12
Figure 1-4: PCIe-7360 Connectors .................................................. 13
Figure 3-1: PCIe-7360 Block Diagram ............................................. 22
Figure 3-2: DI Raw Data Mapping for 8-Bit Data Width ................... 25
Figure 3-3: DI raw data Mapping for 16-Bit Data Width ................... 26
Figure 3-4: DI raw data Mapping for 24-Bit Data Width ................... 27
Figure 3-5: DI raw data Mapping for 32-Bit Data Width ................... 27
Figure 3-6: Phase Shift of Sample Clock ......................................... 28
Figure 3-7: Maximum Data Throughput ........................................... 29
Figure 3-8: Scatter-Gather DMA for Data Transfer .......................... 31
Figure 3-9: DI/DO Sample Clock Architecture ................................. 34
Figure 3-10: DI Continuous Mode Architecture.................................. 37
Figure 3-11: DI Timing Diagram......................................................... 38
Figure 3-12: DO Continuous Mode Architecture ................................ 40
Figure 3-13: DO Timing Diagram ....................................................... 41
Figure 3-14: DI Handshake Mode Architecture.................................. 43
Figure 3-15: DI Handshake Timing Diagram...................................... 44
Figure 3-16: DO Handshake Mode Architecture ................................ 46
Figure 3-17: DO Handshake Timing Diagram.................................... 47
Figure 3-18: DI Burst Handshake Mode Architecture ........................ 49
Figure 3-19: DI Burst Handshake Timing Diagram ............................ 50
Figure 3-20: DO Burst Handshake Mode Architecture....................... 52
Figure 3-21: DO Burst Handshake Timing Diagram .......................... 53
Figure 3-22: DO Burst Handshake 2 Timing Diagram ....................... 53
Figure 3-23: DI Post Trigger............................................................... 54
Figure 3-24: DO Post Trigger............................................................. 55
Figure 3-25: DI Post Trigger with Re-trigger ...................................... 55
Figure 3-26: DO Post Trigger with Re-Trigger ................................... 56
Figure 3-27: DI Gated Trigger ............................................................ 56
Figure 3-28: DO Gated Trigger .......................................................... 57
Figure 3-29: I2C Master of PCIe-7360 ............................................... 62
Figure 3-30: Data Transfer on the I2C Bus ........................................ 63
Figure 3-31: I2C Data Format ............................................................ 64
Figure 3-32: SPI Master of PCIe-7360............................................... 65
Figure 3-33: Data Transfer on SPI Bus.............................................. 66
Figure 3-34: Clock Mode of SCK ....................................................... 66