ADLINK PCIe-7360 - Manual (Page 15)

Introduction 5
PCIe-7360
Internal clock rate
(programmable) 1526 Hz – 100 MHz (100 MHz/ N;
1≤N≤65,535)
Ext. frequency range
Phase shift disabled: 0-200 MHz
Phase shift enabled: 20MHz - 100MHz (see
Note)
Phase shift
Internal clock: N/A
External clock: 80 steps; 1 step = 4.5°
Sample Clock Exporting
Destination
AFI6 (for DO)
AFI7 (for DI)
SMB CLK out
Frequency range
Phase shift disabled: 0-100 MHz
Phase shift enabled: 20MHz - 100MHz (see
Note)
Clock jitter Period jitter: 300 ps
Clock duty cycle 50%
Phase shift resolution
1/80 of external sampled clock period (80
steps; 1 step = 4.5°)
NOTE: NOTE:
When phase shift is enabled, the clock must be continuous and
free-running