ADLINK PCIe-7360 - Manual (Page 73)

Operations 63
PCIe-7360
Address or Data). Figure 3-29 shows the data transfer on the I
2
C
bus.
Figure 3-30: Data Transfer on the I
2
C Bus
I
2
C master of PCIe-7360 supports the clock range from 1.9 kHz to
244.14 kHz. After issuing command to I
2
C slave device, the clock
rate might be changed according the request from I
2
C slave. The
below formula is to calculate the I
2
C clock rate.
F
scl
= 488.28 / (Clk Pre-scale + 1) (kHz),
where Clk Pre-scale = 1 to 255
I
2
C Write Command: the content of Cmd/Addr and Data are
stored in registers I
2
C_A_CA and I
2
C_A_DAT and their byte
counts are indicated by I
2
C CmdAddr Byte Count and Access Byte
Count, respectively.
I
2
C Read Command: the format of Read command is similar with
a write command except that the data part is derived by slave
device.