ADLINK PCIe-7360 - Manual (Page 46)

36 Operations
can be selected from internal or external clock source. The opera-
tion sequences are listed as follows:
Steps:
X
Define DI port configuration (32/24/16/8-bits data width)
X
Define DI logic level configuration (3.3/2.5/1.8 V)
X
Define DI sample clock configuration (internal/external)
Z
If choose internal sampled clock, you can define sam-
pling clock rate to be 100MHz/n (n = 1 to 65535)
Z
If choose external sampled clock, the phase shift func-
tion is available when external clock is a free-running
clock (not a strobe signal) and external clock rate is from
20 to 100 MHz.
X
Define DI starting mode configuration (NoWait or WaitTRIG)
Z
If choose WaitTRIG, you can define start trigger source
to be software trigger or external trigger (DI-Start) from
AFI0 to AFI7.
X
Define DI data count
X
Execute DI DMA Read Command (continuous mode)