ADLINK PCIe-7360 - Manual (Page 20)

10 Introduction
1.3.8 SPI Master Specification
Transfer size of Data 0 - 4 Bytes
Transfer size of Cmd/ Addr 0 - 4 Bytes
Logic families
(programmable)
1.8 V 2.5 V 3.3 V
Input Voltage
Min. V
IH
1.2 V 1.6 V 2.0 V
Max. V
IL
0.63 V 0.7 V 0.8 V
Output Voltage
Min. V
OH
1.6 V 2.3 V 3.1 V
Max. V
OL
0.2 V 0.2 V 0.2 V
Signal
Direction Pin
SCK O AFI0
SDO O AFI1
SDI I AFI2
CS_0 O AFI3
Supported clock rate
(programmable) 244.14 kHz -62.5 MHz,
62.5 MHz / (n + 1); 0 ≤ n ≤ 255
Clock mode
The first bit be transferred
MSB/ LSB
(Default: MSB)
Transfer size of Data 0 - 32 bits
Transfer size of Cmd/ Addr 0 - 32 bits
Dummy size
0 - 15 bits
SPI Slave selection CS_0
Logic families
(programmable)
1.8 V 2.5 V 3.3 V
Input Voltage
Min. V
IH
1.2 V 1.6 V 2 V
Max. V
IL
0.63 V 0.7 V 0.8 V
Output Voltage
Min. V
OH
1.6 V 2.3 V 3.1 V
Max. V
OL
0.2 V 0.2 V 0.2 V
Mode =1
Mode =0