ADLINK PCIe-7360 - Manual (Page 33)

Operations 23
PCIe-7360
level. When connecting PCIe-7360 to a device under test (DUT),
interface voltage levels must be compatible, as follows.
X
V
IH
: The digital input voltage at logic high; senses a binary
one (1)
X V
IL
: The digital input voltage at logic low; senses a binary
zero (0)
X
V
OH
: The digital output voltage at logic high; generates a
binary one (1)
X V
OL
: The digital output voltage at logic low; generates a
binary zero (0)
Table 3-1: Logic Levels
3.3 Digital I/O Configuration
32-channel high-speed digital I/O lines are bi-directional and
divided into four groups. Each group contains 8 channels and can
be configured as input port or output port individually. At power-up,
all I/O lines are preset to input ports. When configuring to digital
output mode, the initial status of digital outputs are in tri-state.
Possible configuration modes are as follows:
Logic Levels 1.8 V 2.5 V
3.3 V
(5 V compatible)
Digital Input
Min. VIH 1.2 V 1.6 V 2 V
Max. VIL 0.63 V 0.7 V 0.8 V
Digital Output
Min. VOH 1.6 V 2.3 V 3.1 V
Max. VOL 0.2 V 0.2 V 0.2 V
Port Channel Power-up status Direction
Port A D0 to D7 Input Input or output
Port B D8 to D15 Input Input or output
Port C D16 to D23 Input Input or output
Port D D24 to D31 Input Input or output