ADLINK PCIe-7360 - Manual (Page 44)

34 Operations
Figure 3-9: DI/DO Sample Clock Architecture
80-step
phase shift
I
AFI7
1/N
DI CLK
Mux
Int. DI sampled clk
80-step
phase shift
DI Sampled CLK
Acquisition
Engine
Int. Timebase
Ext. DI sampled clk
SMB CLK out
I
AFI6
Ext. DO CLK
Mux
E
x
t.
DI
CL
K
Mux
Export. DI/DO CLK
Mux
Export. DI CLK
Mux
80-step
phase shift
AFI6
O
Ex
port. DO CLK
Mux
DO sampled clk
SMB CLK in
DO CLK
Mux
80-step
phase shift
Int. DO sampled clk
1/N
DO Sampled CLK
Generation
Engine
Ext. DO sampled clk
O
AFI7
100MHz
DI sampled clk