ADLINK PCIe-7360 - Manual (Page 48)

38 Operations
Figure 3-11: DI Timing Diagram
DO DMA in Continuous Mode
For the DO pattern generation operation in continuous mode,
PCIe-7360 card can generate digital data to external devices at a
specific update clock rate (DO sample clock). DO sample clock
can be selected from internal or external clock source. The opera-
tion sequences are listed as follows:
Steps:
X Define DO port configuration (32/24/16/8-bits data width)
X Define DO logic level configuration (3.3/2.5/1.8 V)
X Define DO sample clock configuration (internal/external)
Z If choose internal sample clock, you can define sampling
clock rate to be 100MHz/n (n = 1 to 65535)
Z
If choose external sample clock, the phase shift function
is available when external clock rate is 20 to 100 MHz.
X
Define DO exporting sample clock configuration (AFI6/SMB
CLK out)