ADLINK PCIe-7360 - Manual (Page 5)

Table of Contents v
PCIe-7360
Table of Contents
Revision History...................................................................... ii
Preface .................................................................................... iii
List of Figures ....................................................................... vii
List of Tables.......................................................................... ix
1 Introduction ........................................................................ 1
1.1 Features............................................................................... 1
1.2 Applications ......................................................................... 1
1.3 Specifications....................................................................... 2
1.4 Software Support ............................................................ 11
DAQPilot ....................................................................... 11
PCIS-DASK .................................................................. 11
1.5 Schematics, I/O and Indicators.......................................... 12
1.6 Connectors ........................................................................ 12
1.7 LED indicator ..................................................................... 17
2 Getting Started ................................................................. 19
2.1 Unpacking Checklist .......................................................... 19
2.2 Installing the Card.............................................................. 19
2.3 Selecting Cables and Termination Board .......................... 20
3 Operations ........................................................................ 21
3.1 Block Diagram ................................................................... 21
3.2 Programmable Logic Level ................................................ 22
3.3 Digital I/O Configuration..................................................... 23
DI Raw Data Mapping ................................................... 24
3.4 Sample Clock Phase Shift ................................................. 27
3.5 Bus-mastering DMA Data Transfer.................................... 29