Kontron NSN2U IP Network Server User Manual

Page 30

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The memory operational mode is configurable at the channel level. Two modes are

supported: Independent Channel and Mirrored Channel.

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The memory slots of each DDR3 channel from the Intel® Xeon® Processor 5500 Series

are populated on a farthest first fashion. This holds true even for the Independent

Channel mode. Therefore, if A1 is empty, A2 cannot be populated or used.

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The BIOS selects Independent Channel mode by default, which enables all installed

memory on all channels simultaneously.

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Mirrored Channel mode is not available when only one processor is populated (CPU

socket 1).

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If both processor sockets are populated and the installed DIMMs are associated with

both processor sockets, then a given RAS mode is selected only if both of the

processor sockets are populated to conform to that mode.

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The minimum memory population possible is one DIMM in slot A1. In this

configuration, the system operates in the Independent Channel mode. RAS is not

available.

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If both processor sockets are populated, the next upgrade from the Single Channel

mode installs DIMM D1. This configuration results in an optimal memory thermal

spread, as well as Non-Uniform Memory Architecture (NUMA)-aware interleaving. The

BIOS selects the Independent Channel mode of operation.

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If only one processor socket is populated, the next upgrade from the Single Channel

mode is installing DIMM B1 to allow channel interleaving. The system operates in the

Independent Channel mode.

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The DIMM parameter-matching requirements for memory RAS is local to a socket. For

example, while Channels A/B/C can have one match of timing, technology, and size,

channels D/E/F can have a different set of parameters and RAS still functions.

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DDR3 DIMMs on adjacent slots on the same channel do not need to be identical.

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For the Mirrored Channel mode, the memory in channels A and B of socket 1 must be

identical and channel C should be empty. Similarly, the memory in Channels D and E

of Socket 2 must be identical and Channel F should be empty.

a. The minimum population upgrade for the Mirrored Channel mode is DIMM A1, DIMM

B1, DIMM D1, and DIMM E1 with both processor sockets populated. DIMM A1 and DIMM

B1 as a pair must be identical, and so must DIMM D1 and DIMM E1, but the DIMMs

on different processor sockets do not need to be identical.

Failure to comply with these rules results in a switch back to Independent

Channel mode.

b. If Mirrored Channel mode is selected and the third channel of each processor

socket is not empty, the BIOS disables the memory in the third channel of each

processor socket.

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In the Mirrored Channel mode, both sockets must simultaneously satisfy the DIMM

matching rules on their respective adjacent channels. If the DDR3 DIMMs on adjacent

channels of a socket are not identical, the BIOS configures both the processor

sockets to default to the Independent Channel mode. If DIMM D1 and DIMM E1 are not

identical, then the system switches to the Independent Channel Mode.

Installing Memory DIMMs

NOTE: To reduce the risk of electrostatic discharge (ESD) damage to the processor or

the DIMM, be sure to follow these procedures:

Touch the metal chassis before touching the DIMM or server board.

Keep part of your body in contact with the metal chassis to dissipate the static

charge while handling the DIMM.

Avoid moving around unnecessarily.

Use a ground strap attached to the front panel (with the bezel removed).