Achronix Speedster22i PCIe - Manual (Page 78)

UG030, April 26, 2013 78
output [1:0]
c2s_areset_n ;
output [1:0] c2s_aclk_out ;
output [1:0] c2s_arvalid ;
output [71:0] c2s_araddr ;
output [7:0] c2s_arlen ;
output [5:0] c2s_arsize ;
output [1:0] c2s_rready ;
output [1:0] c2s_ruserafull ;
///// MASTER SIDE INTERFACE ////
output m_aclk_out
;
output m_awready ;
output m_wready ;
output m_bvalid ;
output [1:0] m_bresp ;
output m_arready ;
output m_rvalid ;
output [31:0] m_rdata ;
output [1:0] m_rresp ;
output [4:0] m_interrupt ;
///// TAREGT SIDE INTERFACE /////
output t_awvalid
;
output [31:0] t_awaddr ;
output [3:0] t_awlen ;
output [2:0] t_awregion ;
output [2:0] t_awsize ;
output t_wvalid ;
output [127:0] t_wdata ;
output [15:0] t_wstrb ;
output t_wlast ;
output t_bready ;
output t_arvalid ;
output [31:0] t_araddr ;
output [3:0] t_arlen ;
output [2:0] t_arregion ;
output [2:0] t_arsize ;
output t_rready ;
///// MANAGEMENT INTERFACE /////
output
mgmt_pl_link_up_o ;
output mgmt_dl_link_up_o ;
output [15:0] mgmt_cfg_id ;