Achronix Speedster22i PCIe User Manual
Page 74
UG030, April 26, 2013
74
,
t_arready
,
t_araddr
,
t_arlen
,
t_arregion
,
t_arsize
,
t_rvalid
,
t_rready
,
t_rdata
,
t_rresp
,
t_rlast
///// MANAGEMENT INTERFACE /////
,
mgmt_pl_link_up_o
,
mgmt_dl_link_up_o
,
mgmt_cfg_id
,
mgmt_transactions_pending
,
user_interrupt
,
mgmt_rp_leg_int_o
,
pm_power_state
,
pm_l1_enter
,
pm_l1_exit
,
pm_l2_enter
,
pm_l2_enter_ack
,
pm_l2_exit
,
pm_l2_store
,
pm_d3cold_exit
,
pm_d3cold_exit_ack
,
pm_d3cold_restore
,
pm_d3cold_pme_asserted
,
pm_d3cold_n_pme_assert
///// CONFIGURATION REGISTER EXPANSION INTERFACE /////
,
core_cfg_exp_addr
,
core_cfg_exp_wr_en
,
core_cfg_exp_wr_data
,
core_cfg_exp_wr_be
,
core_cfg_exp_rd_en
,
core_cfg_exp_rd_data
,
core_cfg_exp_rd_val
);
/////// PORTS DECLERATION ///////
////// INPUTS ////
input
perst_n
;
//// SERDES SIDE INTERFACE ////
input [7:0]
pcie_refclk_p
;
//// FOR (P-SIDE)