Achronix Speedster22i PCIe - Manual (Page 36)

UG030, April 26, 2013 36
DMA-Side Port Descriptions
AXI Target Interface
Table 4: Target Interface Pin Descriptions
Pin Name Direction Clock Description
t_areset_n
Input t_aclk Active-low asynchronous assert, t_aclk-synchronous
de-assert reset;
Must be asserted when DMA Back End PCI Express
reset is asserted.
t_aclk
Input AXI interface clock; may be a different clock than the
clock used on the PCI Express-side of the AXI DMA
Back-End Core; synchronization techniques are used
to enable support for a wide variety of clock rates
t_awvalid
Output t_aclk
Write Address Channel; Optional AWBURST,
AWLOCK, AWCACHE, AWPROT are not
implemented; AWBURST is always incrementing-
address burst; cache, protected, and exclusive
accesses not supported; see below for t_awregion
information
t_awready
Input t_aclk
t_awregion
[2:0] Output t_aclk
t_awaddr
[31:0] Output t_aclk
t_awlen
[3:0] Output t_aclk
t_awsize
[2:0] Output t_aclk
t_wvalid Output t_aclk
Write Data Channel
t_wready Input t_aclk
t_wdata
[127:0] Output t_aclk
t_wstrb
[15:0] Output t_aclk
t_wlast Output t_aclk
t_bvalid Input t_aclk Write Response Channel; space is reserved in the
master to receive response from all outstanding
write requests, so t_bready is always 1 and does not
need to be used.
t_bready Output t_aclk
t_bresp
[1:0] Input t_aclk
t_arvalid Output t_aclk Read Address Channel; Optional ARBURST,
ARLOCK, ARCACHE, ARPROT are not
implemented; ARBURST is always incrementing-
address burst; cache, protected, and exclusive
accesses not supported; see below for t_arregion
information .
t_arready Input t_aclk
t_arregion
[2:0] Output t_aclk
t_araddr
[31:0] Output t_aclk